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JS28F320J3F75A Datasheet(PDF) 39 Page - Numonyx B.V |
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JS28F320J3F75A Datasheet(HTML) 39 Page - Numonyx B.V |
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39 / 66 page ![]() Jan 2011 Datasheet 208032-03 39 Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC) Note: Issuing the Read Array command to the device while it is actively erasing causes subsequent reads from the device to output invalid data. Valid array data is output only after the block-erase operation has finished. Standby power levels are not be realized until the block-erase operation has finished. Also, asserting RP# aborts the block-erase operation, and array contents at the addressed location are indeterminate. The addressed block should be erased before programming within the block is attempted. 9.5 Blank Check The Blank Check operation determines whether a specified array block is blank (i.e. completely erased). Without Blank Check, Block Erase would be the only other way to ensure a block is completely erased. Blank Check is especially useful in the case of erase operation interrupted by a power loss event. Blank Check can apply to only one block at a time, and no operations other than Status Register Reads are allowed during Blank Check (e.g. reading array data, program, erase etc.). Suspend and resume operations are not supported during Blank Check, nor is Blank Check supported during any suspended operations. Blank Check operations are initiated by writing the Block Blank Check command to the block address. Next, the Blank Check Confirm command is issued along with the same block address. When a successful command sequence is entered, the device automatically enters the Read Status State. The WSM then reads the entire specified block, and determines whether any bit in the block is programmed or over-erased. The status register can be examined for Blank Check progress and errors by reading any address within the block being accessed. During a blank check operation, the Status Register indicates a busy status (SR.7 = 0). Upon completion, the Status Register indicates a ready status (SR.7 = 1). The Status Register should be checked for any errors, and then cleared. If the Blank Check operation fails, which means the block is not completely erased, the Status Register bit SR.5 will be set (“1”). CE# or OE# toggle (during polling) updates the Status Register. The device remains in Status Register Mode until another command is written to the device. After examining the Status Register, it should be cleared by the Clear Status Register command before issuing a new command. Any command can follow once the Blank Check command is complete. 9.6 Suspend and Resume An erase or programming operation can be suspended to perform other operations, and then subsequently resumed. Table 24 shows the Suspend and Resume command bus- cycles. Note: All erase and programming operations require the addressed block to remain unlocked with a valid voltage applied to VPEN throughout the suspend operation. Otherwise, the block-erase or programming operation will abort, setting the appropriate Status Register error bit(s). Also, asserting RP# aborts suspended block-erase and |
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