MP8666DN datasheet(2/11 Pages) MPS

2 / 11 page

MP8666 – 6A, 21V, 600kHz STEP-DOWN WITH SYNCHRONIZABLE GATE DRIVER

MP8666 Rev. 1.21

www.MonolithicPower.com

9/21/2011

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

ORDERING INFORMATION

Part Number*

Package

Top Marking

Free Air Temperature (TA)

MP8666DN

SOIC8E

MP8666DN

–40

°C to +85°C

* For Tape & Reel, add suffix –Z (e.g. MP8666DN–Z);

For RoHS Compliant Packaging, add suffix –LF (e.g. MP8666DN–LF–Z)

PACKAGE REFERENCE

ABSOLUTE MAXIMUM RATINGS (1)

Supply Voltage VIN ....................................... 23V

VSW.........................-0.3V(-5V for < 10ns) to 24V

VBST - VSW....................................................... 6V

All Other Pins.................................–0.3V to +6V

Continuous Power Dissipation

(TA = +25°C)

(2)

SOIC8E...................................................... 2.5W

Junction Temperature...............................150

°C

Lead Temperature ....................................260

°C

Storage Temperature.............. –65

°C to +150°C

Recommended Operating Conditions

(3)

Supply Voltage VIN ...........................4.5V to 21V

Operating Temperature............. –40

°C to +85°C

Thermal Resistance

(4)

θJA

θJC

SOIC8E .................................. 50 ...... 10...

°C/W

Notes:

1) Exceeding these ratings may damage the device.

2) The maximum allowable power dissipation is a function of the

maximum junction temperature TJ(MAX), the junction-to-

ambient thermal resistance θJA, and the ambient temperature

TA. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-

TA)/ θJA. Exceeding the maximum allowable power dissipation

will cause excessive die temperature, and the regulator will go

into thermal shutdown. Internal thermal shutdown circuitry

protects the device from permanent damage.

3) The device is not guaranteed to function outside of its operating

conditions.

4) Measured on JESD51-7, 4-layer PCB.

BST

VCC

EN/SYNC

GND

TOP VIEW

EXPOSED PAD

ON BACKSIDE

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