MP28248 – 3A, 4.2V-20V INPUT, FAST-TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN QFN12 (2X3mm)

MP28248 Rev. 1.0

www.MonolithicPower.com

16

1/5/2012

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© 2012 MPS. All Rights Reserved.

Figure 12: Simplified Ceramic Capacitor Circuit

with DC Blocking Capacitor

Input Capacitor

The input current to the step-down converter is

discontinuous and therefore requires a capacitor

to supply the AC current to the step-down

converter while maintaining the DC input voltage.

Ceramic capacitors are recommended for best

performance and should be placed as close to

X7R ceramic dielectrics are recommended

because they are fairly stable with temperature

fluctuations.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated as follows:

OUT

OUT

CIN

OUT

IN

IN

VV

II

(1

)

VV



 

(17)

where:

OUT

CIN

I

I

2



(18)

For simplification, choose an input capacitor with

an RMS current rating greater than half of the

maximum load current.

The input capacitance value determines the input

voltage ripple of the converter. If there is an input

voltage ripple requirement in the system, choose

the input capacitor that meets the specification.

The input voltage ripple can be estimated as

follows:

OUT

OUT

OUT

IN

SW

IN

IN

IN

IV

V

ΔV=

1-

fC

V

V









(19)

OUT

IN

SW

IN

I

1

ΔV=

4f

C





(20)

Output Capacitor

The output capacitor maintains the DC output

voltage. Use ceramic or POSCAP capacitors for

best results. The output voltage ripple can be

estimated as:



 









OUT

OUT

OUT

ESR

SW

IN

SW

OUT

VV

1

V(1

) (R

)

fL

V

8 f

C

(21)

For ceramic capacitors, the impedance at the

switching

frequency

is

dominated

by

the

capacitance. The output voltage ripple is mainly

caused by the capacitance. For simplification, the

output voltage ripple can be estimated as:



 

 

OUT

OUT

OUT

2

SW

OUT

IN

VV

V(1

)

8f

L C

V

(22)

The output voltage ripple caused by ESR is very

small and requires an external ramp to stabilize

the system. The external ramp can be generated

through resistor R4 and capacitor C4 following

equations 5, 8 and 9.

For POSCAP capacitors, the ESR dominates the

impedance at the switching frequency. The ramp

voltage generated from the ESR is high enough

to stabilize the system and therefore does not

need an external ramp. Use a minimum ESR

value of around 12mΩ to ensure stable converter

operation. For simplification, the output ripple can

be approximated as:



 





OUT

OUT

OUT

ESR

SW

IN

VV

V(1

) R

fL

V

(23)

The application design must also consider the

maximum output capacitor value. If the output

capacitor value is too high, the output voltage

can’t reach the designated value during the soft-

start time, and then the device will fail to regulate.

be approximately by:





O_ MAX

LIM _ AVG

OUT

ss

OUT

C(I

I

) t / V

(24)

time.