MP28254 – SYNCHRONOUS STEP-DOWN CONVERTER WITH INTERNAL MOSFETS

MP28254 Rev. 1.01

www.MonolithicPower.com

9

5/15/2012

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© 2012 MPS. All Rights Reserved.

OPERATION

The MP28254 is a high frequency synchronous

rectified step-down switch mode converter with

built in internal power MOSFETs. It offers a very

compact solution to achieve 4A continuous

output current over a wide input supply range

with excellent load and line regulation.

The MP28254 operates in a fixed frequency,

peak current control mode to regulate the output

voltage. A PWM cycle is initiated by the internal

clock. The integrated high-side power MOSFET

is turned on and remains on until its current

reaches the value set by the COMP voltage.

When the power switch is off, it remains off until

the next clock cycle starts. If, in 90% of one PWM

period, the current in the power MOSFET does

not reach the COMP set current value, the power

MOSFET will be forced to turn off

Power Good Indicator

internally pulled low. When the FB is above

PG function is not used, it can be left open.

Internal Regulator

Most of the internal circuitries are powered from

the 5V internal regulator. This regulator takes the

VIN input and operates in the full VIN range.

When VIN is greater than 5.0V, the output of the

regulator is in full regulation. When VIN is lower

than 5.0V, the output decreases. 0.1uF ceramic

capacitor for decoupling purpose is required.

Error Amplifier

The error amplifier compares the FB pin voltage

with the internal 0.805V reference (REF) and

outputs a current proportional to the difference

between the two. This output current is then used

to charge or discharge the internal compensation

network to form the COMP voltage, which is used

to control the power MOSFET current. The

optimized

internal

compensation

network

minimizes the external component counts and

simplifies the control loop design.

Enable/Sync Control

EN/Sync is a digital control pin that turns the

regulator on and off. Drive EN high to turn on the

regulator, drive it low to turn it off. There is an

internal 1MEG resistor from EN/Sync to GND

thus EN/Sync can be floated to shut down the

chip.

1) Enabled by external logic H/L signal

The chip starts up once the enable signal goes

higher than EN/SYNC input high voltage (2V),

and is shut down when the signal is lower than

EN/SYNC input low voltage (0.4V). To disable

the chip, EN must be pulled low for at least 5µs.

The input is compatible with both CMOS and TTL.

2) Enabled by Vin through voltage divider.

Connect EN with VIN through a resistive voltage

divider for automatic startup as the figure 2

shows.

EN

Figure 2—Enable Divider Circuit

start-up voltage:

R

R

(R

V

V

EN2

EN2

EN1

EN_RISING

IN_START

Ω

Ω

+

⋅

=

M

M

1

||

)

1

||

Ω

Ω

+

⋅

=

M

M

1

||

)

1

||

EN2

EN2

EN1

FALLING

-

EN

IN_STOP

R

R

(R

V

V

Figure 3—Startup Sequence Using EN Divider

3) Synchronized by External Sync Clock Signal

The chip can be synchronized to external clock

range from 300kHz up to 2MHz through this pin

2ms right after output voltage is set, with the

internal clock rising edge synchronized to the

external clock rising edge.