VS1011E datasheet(21/48 Pages) ETC2

21 / 48 page

VS1011e

SPI BUSES

After the word has been shifted in and the last clock has been sent, XCS should be pulled high

to end the WRITE sequence.

After the last bit has been sent, DREQ is driven low for the duration of the register update,

marked “execution” in the ﬁgure. The time varies depending on the register and its contents

(see table in Chapter 8.6 for details). If the maximum time is longer than what it takes from

the microcontroller to feed the next SCI command or SDI byte, it is not allowed to ﬁnish a new

SCI/SDI operation before DREQ has risen up again.

7.6

SPI Timing Diagram

XCS

SCK

tXCSS

tXCSH

tWL

tWH

tSU

tDIS

tXCS

Figure 11: SPI Timing Diagram.

Symbol

Min

Max

Unit

tXCSS

tSU

-26

CLKI cycles

tWL

CLKI cycles

tWH

CLKI cycles

2 (+ 25ns1)

CLKI cycles

tXCSH

-26

tXCS

CLKI cycles

tDIS

1 25ns is when pin loaded with 100pF capacitance. The time is shorter with lower capacitance.

Note: As tWL and tWH, as well as tH require at least 2 clock cycles, the maximum speed for the

SPI bus that can be used for read operations is 1/6 of VS1011e’s external clock speed CLKI.

For write operations maximum speed is 1/4 of CLKI. Because of asynchronous clocks between

the systems, the actual speed must be a bit slower to allow timing variations.

Note: Negative numbers mean that the signal can change in different order from what is shown

in the diagram.

Version: 1.10, 2012-02-29

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