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AM79C30AVC Datasheet(PDF) 80 Page - Advanced Micro Devices |
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AM79C30AVC Datasheet(HTML) 80 Page - Advanced Micro Devices |
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80 / 101 page  80 Am79C30A/32A Data Sheet Microprocessor Read/Write Timing Microprocessor Read Timing Microprocessor Write Timing Notes: 1. The read/write recovery time of 200 ns holds in all cases except when a write command register operation is followed by a read data register operation when accessing the MAP coefficient RAM. This operation requires a minimum recovery time of 450 ns. 2. Successive reads of the D-Channel Receive Buffer require a minimum cycle time (tRLRH + tRHRL) of 480 ns. 3. Read access time is measured from the falling edge of CS or the falling edge of RD, whichever occurs last. 4. CS may go Low before either RD or WR goes Low. 5. In minimal systems, CS may be tied Low. 6. Read and write indirect register operations cannot be mixed without at least one write command register operation between them. 7. CS may go High before either RD or WR goes High. 8. If CS goes High before WR goes High, the minimum Address Hold time becomes 12 ns. 9. RD and WR pulse width, Address setup and hold, and Data setup and hold timing are measured from the points where both CS and RD or WR are Low simultaneously. Parameter Symbol Parameter Description Min Max Units tRLRH RD Pulse Width 200 ns tRHRL Read Recovery Time (Notes 1, 2) 200 ns tAVRL Address Valid to RD Low 20 ns tAHRH Address Hold After RD High 10 ns tRHCH RD High to CS High (Note 7) 0 ns tRACC Read Access Time (Note 3) 80 ns tRHDZ RD High to Data Hi-Z 50 ns tRDCS RD Low to CS Low (Note 4) 30 ns Parameter Symbol Parameter Description Min Max Units tWLWH WR Pulse Width 200 ns tWHWL Write Recovery Time (Note 1) 200 ns tAVWL Address Valid to WR Low 20 ns tAHWH Address Hold After WR High (Note 8) 10 ns tWHCH WR High to CS High (Note 7) 0 ns tDSWH Data Setup to WR High 100 ns tDHWH Data Hold After WR High 10 ns tWRCS WR Low to CS Low (Note 4) 30 ns |
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