AM79C940JCW datasheet(46/122 Pages) AMD

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AMD

Am79C940

Other Data Registers

BYPASS REG (1 bit)

Device Identification Register (32 bits)

Bits 31–28: Version (4 bits)

Bits 27–12: Part number (16 bits) is 9400H

Bits 11–1:

Manufacturer ID (11 bits).

The manufacturer ID code for AMD is

00000000001 in accordance with

JEDEC Publication 106-A.

Bit 0:

Always a logic 1

SLAVE ACCESS OPERATION

Internal register accesses are based on a 2 or 3 SCLK

cycle duration, dependent on the state of the

TC input

pin.

TC must be externally pulled low to force the MACE

device to perform a 3-cycle access.

TC is internally

pulled high if left unconnected, to configure the 2-cycle

access by default.

All register accesses are byte wide with the exception of

the data path to and from the internal FIFOs.

Data exchanges to/from register locations will take

place over the appropriate half of the data bus to suit the

host memory organization (as programmed by the

BSWP bit in the BIU Configuration Control register).

The

BE0, BE1 and EOF signals are provided to allow

control of the data flow to and from the FIFOs. Byte read

operations from the Receive FIFO cause data to be du-

plicated on both the upper and lower bytes of the data

bus. Byte write operations to the Transmit FIFO must

use the

BE0 and BE1 inputs to define the active data

byte to the MACE device.

Read Access

Details of the read access timing are located in the AC

Waveforms section, Host System Interface, figures:

Two-Cycle Receive FIFO/Register Read Timing and

Three-Cycle Receive FIFO/Register Read Timing.

TC can be dynamically changed on a cycle by cycle ba-

sis to program the slave cycle execution for two (

TC =

HIGH) or three (

TC = LOW) SCLK cycles. TC must be

stable by the falling edge of SCLK (EDSEL = High) in S0

at the start of a cycle, and should only be changed in S0

in a multiple cycle burst.

A read cycle is initiated when either

CS or FDS is sam-

pled low on the falling edge of SCLK at S0.

FDS and CS

must be asserted exclusively. If they are active simulta-

neously when sampled, the MACE device will not exe-

cute any read or write cycle.

CS is low, a Register Address read will take place. The

state of the ADD4–0 will be used to commence decod-

ing of the appropriate internal register/FIFO.

FDS is low, a FIFO Direct read will take place from the

RCVFIFO. The state of the ADD4–0 bus is irrelevant for

the FIFO Direct mode.

With either the

CS or FDS input active, the state of the

ADD0-4 (for Register Address reads), R/

W (high to indi-

cate a read cycle),

BE0 and BE1 will also be latched on

the falling (EDSEL = HIGH) edge of SCLK at S0.

From the falling edge of SCLK in S1 (EDSEL = HIGH),

the MACE device will drive data on DBUS15–0 and acti-

vate the

DTV output (providing the read cycle completed

successfully). If the cycle read the last byte/word of data

for a specific frame from the RCVFIFO, the MACE de-

vice will also assert the

EOF signal. DBUS15–0, DTV

and

EOF will be guaranteed valid and can be sampled

on the falling (EDSEL = HIGH) edge of SCLK at S2.

If the Register Address mode is being used to access

the RCVFIFO, once

EOF is asserted during the last

byte/word read for the frame, the Receive Frame Status

can be read in one of two ways. The Register Address

mode can be continued, by placing the appropriate ad-

dress (00110b) on the address bus and executing four

read cycles (

CS active) on the Receive Frame Status lo-

cation. In this case, additional Register Address read re-

quests from the RCVFIFO will be ignored, and no

DTV

returned, until all four bytes of the Receive Frame Status

read can be performed, which will effectively route the

Receive Frame Status through the RCVFIFO location.

This mechanism is explained in more detail below.

If the FIFO Direct mode is used, the Receive Frame

Status can be read directly from the RCVFIFO by con-

tinuing to execute read cycles (by asserting

FDS low

and R/

W high) after EOF is asserted indicating the last

byte/word read for the frame. Each of the four bytes of

Receive Frame Status will appear on both halves of the

data bus, as if the actual Receive Frame Status register

were being accessed. Alternatively, the status can be

read as normal using the Register Address mode by

placing the appropriate address (00110b) on the ad-

dress bus and executing four read cycles (

CS active).

Either the FIFO Direct or Register Address modes can

be interleaved at any time to read the Receive Frame

Status, although this is considered unlikely due to the

additional overhead it requires. In either case, no addi-

tional data will be read from the RCVFIFO until the Re-

ceive Frame Status has been read, as four bytes

appended to the end of the packet when using the FIFO

Direct mode, or as four bytes from the Receive Frame

Status location when using the Register Address mode.

EOF will only be driven by the MACE device when read-

ing received packet data from the RCVFIFO. At all other

times, including reading the Receive Frame Status

AM79C940JCW Datasheet(PDF) 46 Page - Advanced Micro Devices

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