AM188ES-40VCSLASHW datasheet(32/102 Pages) AMD

32 / 102 page

Am186/188ES and Am186/188ESLV Microcontrollers

PRELIMIN ARY

generated for 1.5 clock cycles with an adequate

deassertion period to ensure that overall auto refresh

cycle time is met.

This signal functions like the RFSH signal in the

Am186EM and Am188EM microcontrollers except that

the DRAM row address is not driven on DRAM

refreshes. This pin is not three-stated during a bus hold

condition.

NMI

Nonmaskable Interrupt (input, synchronous,

edge-sensitive)

This pin indicates to the microcontroller that an

interrupt request has occurred. The NMI signal is the

highest priority hardware interrupt and, unlike the

I N T 6–I NT 0 pin s , cann ot be m a sked. Th e

microcontroller always transfers program execution to

the location specified by the nonmaskable interrupt

vector in the microcontroller interrupt vector table when

NMI is asserted.

Although NMI is the highest priority interrupt source, it

does not participate in the priority resolution process of

the maskable interrupts. There is no bit associated with

NMI in the interrupt in-service or interrupt request

registers. This means that a new NMI request can

interrupt an executing NMI interrupt service routine. As

with all hardware interrupts, the IF (interrupt flag) is

cleared when the processor takes the interrupt,

disabling the maskable interrupt sources. However, if

maskable interrupts are re-enabled by software in the

NMI interrupt service routine, via the STI instruction for

example, the fact that an NMI is currently in service

does not have any effect on the priority resolution of

maskable interrupt requests. For this reason, it is

strongly advised that the interrupt service routine for

NMI should not enable the maskable interrupts.

An NMI transition from Low to High is latched and

synchronized internally, and it initiates the interrupt at

the next instruction boundary. To guarantee that the

interrupt is recognized, the NMI pin must be asserted

for at least one CLKOUTA period.

PCS1–PCS0

(PCS1/PIO17, PCS0/PIO16)

Peripheral Chip Selects (output, synchronous)

These pins indicate to the system that a memory

access is in progress to the corresponding region of the

peripheral memory block (either I/O or memory

address space). The base address of the peripheral

memory block is programmable. PCS3–PCS0 are held

High during a bus hold condition. They are also held

High during reset.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asserts over a 256-

byte address range, which is twice the address range

covered by peripheral chip selects in the 80C186 and

80C188 microcontrollers.

PCS2/CTS1/ENRX1/PIO18

Peripheral Chip Select 2 (output, synchronous)

Clear-to-Send 1 (input, asynchronous)

Enable-Receiver-Request 1 (input, asynchronous)

PCS2—This pin provides the Peripheral Chip Select 2

signal to the system when hardware flow control is not

enabled for asynchronous serial port 1. The PCS2

signal indicates to the system that a memory access is

in progress to the corresponding region of the

peripheral memory block (either I/O or memory

address space). The base address of the peripheral

memory block is programmable. PCS2 is held High

during a bus hold or reset condition.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asserts over a 256-

byte address range, which is twice the address range

covered by peripheral chip selects in the 80C186 and

80C188 microcontrollers.

CTS1—This pin provides the Clear to Send signal for

asynchronous serial port 1 when the ENRX1 bit in the

AUXCON register is 0 and hardware flow control is

enabled for the port (FC bit in the serial port 1 control

r egister is s e t) . T he C T S 1 si g nal gat es the

transmission of data from the associated serial port

transmit register. When CTS1 is asserted, the

transmitter begins transmission of a frame of data, if

any is available. If CTS1 is deasserted, the transmitter

holds the data in the serial port transmit register. The

value of CTS1 is checked only at the beginning of the

transmission of the frame.

ENRX1—This pin provides the Enable Receiver

Request for asynchronous serial port 1 when the

ENRX1 bit in the AUXCON register is 1 and hardware

flow control is enabled for the port (FC bit in the serial

port 1 control register is set). The ENRX1 signal

enables the receiver for the associated serial port.

PCS3/RTS1/RTR1/PIO19

Peripheral Chip Select 3 (output, synchronous)

Ready-to-Send 1 (output, asynchronous)

Ready-to-Receive 1 (output, asynchronous)

PCS3—This pin provides the Peripheral Chip Select 3

signal to the system when hardware flow control is not

enabled for asynchronous serial port 1. The PCS3

signal indicates to the system that a memory access is

in progress to the corresponding region of the

peripheral memory block (either I/O or memory

address space). The base address of the peripheral

memory block is programmable. PCS3 is held High

during a bus hold or reset condition.

AM188ES-40VC/W Datasheet(PDF) 32 Page - Advanced Micro Devices

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