Device options

L9777

18/25

Doc ID 13496 Rev 2

6

Device options

6.1

Option A

This is the standard configuration with VDD output capable to source up to 100 mA to an

external load with low dropout (400 mV max.) and double reset function provided (NMI and

RESET output).

Note that as we can see in absolute section VDD and TIMING pin are capable to sustain

only short to VI pin.

With this option input digital pins VDD_EN and WD_EN are both pulled up by 5 µA typ

current source (minimum quiescent current is 110 µA typ.).

6.2

Option B

With this option VDD and TIMING pins are both capable to sustain short to 40V regardless

of VI battery voltage. To provide this feature a series diode is introduced between VI pin and

VDD power PMOS source. In this configuration current capability on VDD output is scaled

down to 50 mA while dropout voltage increases to 1.5V (Max). All other features are un-

changed and double reset capability is maintained.

In option B VDD_EN and WD_EN are both pulled down with 10 µA typ internal current

source so minimum quiescent current is reduced to 100 µA typ.

6.3

Option C

Using option C VDD is capable to sustain short to 40 V as in option B. VDD output current is

scaled down to 50 mA and dropout increase up to 1.5 V (Max).

Double reset feature is removed and RESET pin is used to monitor VDD output voltage

(VDD_LOW pin). A spike dependent filter time similar to VCC main regulator is provided and

same low voltage reset specifications applies to bipolar output driver (VDD_LOW driver).

For this reason TIMING pin is no more used and can be left floating or shorted to ground.

Note that NMI output pin behaves normally as in option A and becomes the main reset

signal for VCC and watchdog monitor.

As in option B VDD_EN and WD_EN are both pulled down with 10 µA typ internal current

source so minimum quiescent current is reduced to 100 µA typ.