STA333BW datasheet(29/68 Pages) STMICROELECTRONICS

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STA333BW

FFX compensating pulse size register

Overcurrent warning adjustment bypass

The OCRB is used to indicate how STA333BW behaves when an overcurrent warning

condition occurs. If OCRB = 0 and the overcurrent condition happens, the power control

block forces an adjustment to the modulation limit (default is -3 dB) in an attempt to

eliminate the overcurrent warning condition. Once the overcurrent warning clipping

adjustment is applied, it remains in this state until reset is applied or OCRB is set to 1. The

level of adjustment can be changed via the TWOCL (thermal warning / overcurrent limit)

setting at address 0x37 of the user defined coefficient RAM (Section 7.7.7 on page 55). The

OCRB can be enabled when the output bridge is already on.

7.1.4

Configuration register D (addr 0x03)

High-pass filter bypass

Table 24. FFX compensating pulse size bits

Bit

R/W

RST

Name

Description

2R/W

CSZ0

When OM[1,0] = 11, this register determines the size

of the FFX compensating pulse from 0 clock ticks to

15 clock periods.

3R/W

CSZ1

4R/W

CSZ2

5R/W

CSZ3

Table 25. Compensating pulse size

CSZ[3:0]

Compensating pulse size

0000

0 ns (0 tick) compensating pulse size

0001

20 ns (1 tick) clock period compensating pulse size

……

1111

300 ns (15 tick) clock period compensating pulse size

Table 26. Overcurrent warning bypass

Bit

R/W

RST

Name

Description

R/W

OCRB

0: overcurrent warning adjustment enabled

1: overcurrent warning adjustment disabled

SME

ZDE

DRC

BQL

PSL

DSPB

DEMP

HPB

Table 27. High-pass filter bypass

Bit

R/W

RST

Name

Description

R/W

HPB

1: bypass internal AC coupling digital high-pass filter

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