PIC18F4550EMLSQTP datasheet(39/430 Pages) MICROCHIP

39 / 430 page

Preliminary

DS39632D-page 37

PIC18F2455/2550/4455/4550

FIGURE 3-1:

TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 3-2:

TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

3.2.3

RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer; the primary clock is shut down.

When using the INTRC source, this mode provides the

best power conservation of all the Run modes while still

executing code. It works well for user applications

which are not highly timing sensitive or do not require

high-speed clocks at all times.

If the primary clock source is the internal oscillator

block (either INTRC or INTOSC), there are no distin-

guishable differences between the PRI_RUN and

RC_RUN modes during execution. However, a clock

switch delay will occur during entry to and exit from

RC_RUN mode. Therefore, if the primary clock source

is the internal oscillator block, the use of RC_RUN

mode is not recommended.

This mode is entered by setting SCS1 to ‘1’. Although

it is ignored, it is recommended that SCS0 also be

cleared; this is to maintain software compatibility with

future devices. When the clock source is switched to

the INTOSC multiplexer (see Figure 3-3), the primary

oscillator is shut down and the OSTS bit is cleared. The

IRCF bits may be modified at any time to immediately

change the clock speed.

OSC1

Peripheral

Program

T1OSI

Counter

Clock

CPU

Clock

PC + 2

n-1

Clock Transition(1)

PC + 4

Note

Clock transition typically occurs within 2-4 TOSC.

Q3 Q4

OSC1

Peripheral

Program

T1OSI

PLL Clock

PC + 4

Output

CPU Clock

PC + 2

Clock

Counter

Note

TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

Clock transition typically occurs within 2-4 TOSC.

SCS1:SCS0 bits Changed

TPLL(1)

n-1

Clock(2)

OSTS bit Set

Transition

TOST(1)

Note:

Caution should be used when modifying a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

PIC18F4550EMLSQTP Datasheet(PDF) 39 Page - Microchip Technology

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