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STM8S005C6T6C Datasheet(PDF) 43 Page - STMicroelectronics |
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STM8S005C6T6C Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 103 page ![]() Vector address Wakeup from active-halt mode Wakeup from halt mode Description Source block IRQ no. 0x00 8044 - - Update/ overflow TIM3 15 0x00 8048 - - Capture/ compare TIM3 16 0x00 804C - - Reserved 17 0x00 8050 - - Reserved 18 0x00 8054 Yes Yes I 2C interrupt I 2C 19 0x00 8058 - - Tx complete UART2 20 0x00 805C - - Receive register DATA FULL UART2 21 0x00 8060 - - ADC1 end of conversion/ analog watchdog interrupt ADC1 22 0x00 8064 - - TIM update/ overflow TIM 23 0x00 8068 - - EOP/ WR_PG_DIS Flash 24 0x00 806C to 0x00 807C Reserved (1) Except PA1 43/103 DocID022186 Rev 3 Interrupt vector mapping STM8S005K6 STM8S005C6 |
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