STM32F217VG datasheet(54/175 Pages) STMICROELECTRONICS

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Pinouts and pin description

STM32F21xxx

54/175

DocID17050 Rev 9

VSS

-99 143 171 C6

RFU

(7)

64 100 144 172 C5

VDD

- 173 D4

PI4

I/O FT

TIM8_BKIN, DCMI_D5,

EVENTOUT

- 174 C4

PI5

I/O FT

TIM8_CH1, DCMI_VSYNC,

EVENTOUT

- 175 C3

PI6

I/O FT

TIM8_CH2, DCMI_D6,

EVENTOUT

- 176 C2

PI7

I/O FT

TIM8_CH3, DCMI_D7,

EVENTOUT

1. Function availability depends on the chosen device.

2. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a

maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED).

3. Main function after the first backup domain power-up. Later on, it depends on the contents of the RTC registers even after

reset (because these registers are not reset by the main reset). For details on how to manage these I/Os, refer to the RTC

website: www.st.com.

4. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).

5. If the device is delivered in an UFBGA176 package and if the REGOFF pin is set to VDD (Regulator OFF), then PA0 is used

as an internal Reset (active low).

6. FSMC_NL pin is also named FSMC_NADV on memory devices.

7. RFU means “reserved for future use”. This pin can be tied to VDD,VSS or left unconnected.

Table 7. STM32F21x pin and ball definitions (continued)

Pins

Pin name

(function after

reset)(1)

Alternate functions

Additional

functions

Table 8. FSMC pin definition

Pins

FSMC

LQFP100

NOR/PSRAM/S

RAM

NOR/PSRAM Mux

NAND 16 bit

PE2

A23

Yes

PE3

A19

Yes

PE4

A20

Yes

PE5

A21

Yes

PE6

A22

Yes

PF0

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