LMZ10501SH datasheet(16/25 Pages) TI

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LMZ10501

SNVS677D – MAY 2011 – REVISED MARCH 2013

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OUTPUT VOLTAGE ACCURACY OPTIMIZATION

Each nano module is optimized to achieve high VOUT accuracy. Equation 1 shows that, by design, the output

voltage is a function of the VCON voltage and the gain from VCON to VFB. The voltage at VCON is derived from

VREF. Therefore, as shown in Equation 3, the accuracy of the output voltage is a function of the VREF x GAIN

product as well as the tolerance of the RT and RB resistors. The typical VREF x GAIN product by design is 5.875V.

Each nano module's VREF voltage is trimmed so that this product is as close to the ideal 5.875V value as

possible, achieving high VOUT accuracy. See the Electrical Specifications section for the VREF x GAIN product

tolerance limits.

DYNAMIC OUTPUT VOLTAGE SCALING

The VCON pin on the LMZ10501 can be driven externally by a DAC to scale the output voltage dynamically. The

output voltage VOUT = 2.5V/V x VCON. When driving VCON with a source different than VREF place a 1.5kΩ resistor

in series with the VCON pin. Current limiting the external VCON helps to protect this pin and allows the VCON

capacitor to be fully discharged to 0V after fault conditions.

INTEGRATED INDUCTOR

The LMZ10501 uses a Low Temperature Co-fired Ceramic (LTCC) type 2.6 µH inductor with over 1.2A DC

current rating and soft saturation profile for up to 2A. This inductor allows for the 1.425mm maximum package

height providing an easy to use, compact solution with reduced EMI.

INPUT AND OUTPUT CAPACITOR SELECTION

The LMZ10501 is designed for use with low ESR multi-layer ceramic capacitors (MLCC) for its input and output

filters. Using a 10 µF 0603 or 0805 with 6.3V or 10V rating ceramic input capacitor typically provides sufficient

VIN bypass. Use of multiple 4.7 µF or 2.2µF capacitors can also be considered. Ceramic capacitors with X5R and

X7R temperature characteristics are recommended for both input and output filters. These provide an optimal

balance between small size, cost, reliability, and performance for space sensitive applications.

The DC voltage bias characteristics of the capacitors must be considered when selecting the DC voltage rating

and case size of these components. The effective capacitance of an MLCC is typically reduced by the DC

voltage bias applied across its terminals. For example, a typical 0805 case size X5R 6.3V 10 µF ceramic

capacitor may only have 4.8 µF left in it when a 5.0V DC bias is applied. Similarly, a typical 0603 case size X5R

6.3V 10 µF ceramic capacitor may only have 2.4 µF at the same 5.0V DC. Smaller case size capacitors may

have even larger percentage drop in value with DC bias.

The optimum output capacitance value is application dependent. Too small output capacitance can lead to

instability due to lower loop phase margin. On the other hand, if the output capacitor is too large, it may prevent

the output voltage from reaching the 0.375V required voltage level at the end of the startup sequence. In such

cases, the output short circuit protection can be engaged and the nano module will enter a hiccup mode as

described in the OUTPUT SHORT CIRCUIT PROTECTION section. Table 1 sets the minimum output

capacitance for stability and maximum output capacitance for proper startup for various output voltage settings.

Note that the maximum COUT value in Table 1 assumes that the filter capacitance on VCON is the maximum

recommended value of 1nF and the RT resistor value is less than 300kΩ. Lower VCON capacitance can extend

the maximum COUT range. There is no great performance benefit in using excessive COUT values.

Table 1. Output Capacitance Range

Output Voltage

Minimum

Suggested

Maximum

COUT

0.6V

4.7µF

10µF

47µF

1.0V

3.3µF

10µF

47µF

1.2V

3.3µF

10µF

47µF

1.8V

3.3µF

10µF

68µF

2.5V

3.3µF

10µF

100µF

3.3V

3.3µF

10µF

100µF

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