11

Table 3. AC Electrical Specifications

.

Parameter

Symbol

Min.

Typ.

Max.

Units

Notes

Motion Delay after Reset

50

ms

From RESET register write to valid motion

Forced Rest Enable

1

s

From Rest Mode (RM) bits set to target

rest mode

Wake from Forced Rest

1

s

From Rest Mode (RM) bits cleared to

valid motion

Power Down

50

ms

From PD active (when bit 1 of register

0 x 0d is set) to low current

Wake from Power Down

55

ms

Through RESET register 0 x 3a.

From PD inactive to valid motion

MISO Rise Time

60

200

ns

MISO Fall Time

40

200

ns

MISO Delay after SCLK

120

ns

From SCLK falling edge to MISO data valid,

no load conditions

MISO Hold Time

250

ns

Data held until next falling SCLK edge

MOSI Hold Time

200

ns

Amount of time data is valid after SCLK

rising edge

MOSI Setup Time

120

ns

From data valid to SCLK rising edge

SPI Time between Write

Commands

30

s

From rising SCLK for last bit of the first data

byte, Commands to rising SCLK for last bit

of the second data byte

SPI Time between Write

and Read Commands

20

s

From rising SCLK f or last bit of the first

data byte, to rising SCLK for last bit of the

second address byte

SPI Time between Read and

Subsequent Commands

250

ns

From rising SCLK for last bit of the first data

byte, to falling SCLK for the first bit of the

next address

SPI Read Address-Data

Delay

4

s

From rising SCLK for last bit of the address

byte, to falling SCLK for first bit of data

being read

NCS Inactive after Motion

Burst

250

ns

Minimum NCS inactive time after motion

burst before next SPI usage

NCS to SCLK Active

120

ns

From NCS falling edge to first SCLK falling

edge

SCLK to NCS Inactive

(For Write Operation)

120

ns

From last SCLK rising edge to NCS rising

edge, for valid MISO data transfer

SCLK to NCS Inactive

(For Read Operation)

20

s

From last SCLK rising edge to NCS rising

edge, for valid MISO data transfer

NCS to MISO high-Z

250

ns

From NCS rising edge to MISO high-Z state

Transient Supply Current

60

mA

Max supply current during a VDD ramp

from 0 to VDD with min 150

s and max 20

ms rise time. (Does not include charging

currents for bypass capacitors.)

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PixArt Imaging Inc.

PixArt Imaging Inc.

ADNS-3000 Low Power Optical Mouse Sensor