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PAC7010LU Specification Spec.

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5

UART interface:

MCU

PAC7010

TxD

RxD

Clock

(16M~40Mhz)

5.1

Baud Rate Control

Baud Rate (bps) = Sysclk/Reg_Div, which Reg_Div is a 12 bits divider.

Default baud rate is 19200bps @27Mhz system clock.

Maximum baud rate = 5Mbps

The minimum bit rate is limited by the formula, object data count * object number * frame rate * 12 bps.

5.2

UART Timing Diagram:

D0

D1

D2

D3

D4

D5

D6

D7

Start Bit

Stop Bit

Data (8 bit)

Start bit: 1 bit

Stop bit: 1 bit

Data:

8 bit

Non use parity bit

Note: Host write registers by UART command. The interval timing between byte to next byte must be

wait two bits.

D0

D1

D2

D3

D4

D5

D6

D7

Start Bit

Stop Bit

Data (8 bit)

D0

D1

D2

D3

D4

D5

D6

D7

Start Bit

Stop Bit

Data (8 bit)

wait 2 bits