64GA106 datasheet(252/330 Pages) MICROCHIP

252 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 252

 2010 Microchip Technology Inc.

25.2.2

ON-CHIP REGULATOR AND POR

When the voltage regulator is enabled, it takes approxi-

mately 10

s for it to generate output. During this time,

designated as TVREG, code execution is disabled. TVREG

is applied every time the device resumes operation after

any power-down, including Sleep mode. The length of

TVREG is determined by the PMSLP bit (RCON<8>), as

described in Section 25.2.5 “Voltage Regulator

Standby Mode”

If the regulator is disabled, a separate Power-up Timer

(PWRT) is automatically enabled. The PWRT adds a

fixed delay of 64 ms nominal delay at device start-up

(POR or BOR only). When waking up from Sleep with

the regulator disabled, the PMSLP bit determines the

wake-up time. When operating with the regulator

disabled, setting PMSLP can decrease the device

wake-up time.

25.2.3

ON-CHIP REGULATOR AND BOR

When

the

on-chip

regulator

enabled,

PIC24FJ256GA110 family devices also have a simple

brown-out capability. If the voltage supplied to the reg-

ulator is inadequate to maintain the tracking level, the

regulator Reset circuitry will generate a Brown-out

Reset. This event is captured by the BOR flag bit

(RCON<1>). The brown-out voltage specifications are

provided in the “PIC24FJ Family Reference Manual”,

Section 7. “Reset”

(DS39712).

25.2.4

POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. If the application does not

use the regulator, then strict power-up conditions must

be adhered to. While powering up, VDDCORE must

never exceed VDD by 0.3 volts.

25.2.5

VOLTAGE REGULATOR STANDBY

MODE

When enabled, the on-chip regulator always consumes

a small incremental amount of current over IDD/IPD,

including when the device is in Sleep mode, even

though the core digital logic does not require power. To

provide additional savings in applications where power

resources are critical, the regulator automatically

disables itself whenever the device goes into Sleep

mode. This feature is controlled by the PMSLP bit

(RCON<8>). By default, the bit is cleared, which

removes power from the Flash program memory, and

thus, enables Standby mode. When waking up from

Standby mode, the regulator must wait for TVREG to

expire before wake-up. This extra time is needed to

ensure that the regulator can source enough current to

power the Flash memory.

For applications which require a faster wake-up time, it

is possible to disable regulator Standby mode. The

PMSLP bit can be set to turn off Standby mode so that

the Flash stays powered when in Sleep mode and the

device can wake-up without waiting for TVREG. When

PMSLP is set, the power consumption while in Sleep

mode, will be approximately 40

A higher than power

consumption when the regulator is allowed to enter

Standby mode.

25.3

Watchdog Timer (WDT)

For PIC24FJ256GA110 family devices, the WDT is

driven by the LPRC Oscillator. When the WDT is

enabled, the clock source is also enabled.

The nominal WDT clock source from LPRC is 31 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the FWPSA Configuration bit.

With a 31 kHz input, the prescaler yields a nominal

WDT time-out period (TWDT) of 1 ms in 5-bit mode or

4 ms in 7-bit mode.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPS<3:0>

Configuration bits (CW1<3:0>), which allow the selec-

tion of a total of 16 settings, from 1:1 to 1:32,768. Using

the prescaler and postscaler, time-out periods ranging

from 1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSC bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

• When a PWRSAV instruction is executed

(i.e., Sleep or Idle mode is entered)

• When the device exits Sleep or Idle mode to

resume normal operation

•By a CLRWDT instruction during normal execution

If the WDT is enabled, it will continue to run during

Sleep or Idle modes. When the WDT time-out occurs,

the device will wake the device and code execution will

continue from where the PWRSAV instruction was exe-

cuted. The corresponding SLEEP or IDLE bits

(RCON<3:2>) will need to be cleared in software after

the device wakes up.

The WDT Flag bit, WDTO (RCON<4>), is not auto-

matically cleared following a WDT time-out. To detect

subsequent WDT events, the flag must be cleared in

software.

Note:

For more information, see Section 28.0

“Electrical Characteristics”

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

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