PIC16F84A datasheet(23/337 Pages) MICROCHIP

23 / 337 page

DS30234D-page 23

PIC16C6X

4.2.2

SPECIAL FUNCTION REGISTERS:

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The special function registers can be classiﬁed into two

sets (core and peripheral). The registers associated

with the “core” functions are described in this section

and those related to the operation of the peripheral fea-

tures are described in the section of that peripheral fea-

ture.

TABLE 4-1:

SPECIAL FUNCTION REGISTERS FOR THE PIC16C61

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR

Value on

all other

resets(3)

Bank 0

00h(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

01h

TMR0

Timer0 module’s register

xxxx xxxx

uuuu uuuu

02h(1)

PCL

Program Counter's (PC) Least Signiﬁcant Byte

0000 0000

03h(1)

STATUS

IRP(4)

RP1(4)

RP0

ZDC

0001 1xxx

000q quuu

04h(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

05h

PORTA

—

PORTA Data Latch when written: PORTA pins when read

---x xxxx

---u uuuu

06h

PORTB

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx

uuuu uuuu

07h

—

Unimplemented

—

08h

—

Unimplemented

—

09h

—

Unimplemented

—

0Ah(1,2)

PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0Bh(1)

INTCON

GIE

—

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0-00 000x

0-00 000u

Bank 1

80h(1)

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

81h

OPTION

RBPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

82h(1)

PCL

Program Counter's (PC) Least Signiﬁcant Byte

0000 0000

83h(1)

STATUS

IRP(4)

RP1(4)

RP0

ZDC

0001 1xxx

000q quuu

84h(1)

FSR

Indirect data memory address pointer

xxxx xxxx

uuuu uuuu

85h

TRISA

—

PORTA Data Direction Register

---1 1111

86h

TRISB

PORTB Data Direction Control Register

1111 1111

87h

–

Unimplemented

—

88h

–

Unimplemented

—

89h

–

Unimplemented

—

8Ah(1,2)

PCLATH

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

8Bh(1)

INTCON

GIE

—

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0-00 000x

0-00 000u

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'.

Shaded locations are unimplemented and read as ‘0’

Note 1:

These registers can be addressed from either bank.

The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose con-

tents are transferred to the upper byte of the program counter. (PC<12:8>)

Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset.

The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.

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