PIC16F84A datasheet(120/337 Pages) MICROCHIP

120 / 337 page

PIC16C6X

DS30234D-page 120

12.4

USART Synchronous Slave Mode

Synchronous Slave Mode differs from Master Mode in

the fact that the shift clock is supplied externally at the

CK pin (instead of being supplied internally in master

mode). This allows the device to transfer or receive

data while in SLEEP mode. Slave mode is entered by

clearing bit CSRC (TXSTA<7>).

12.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the synchronous master and slave

modes are identical except in the case of the SLEEP

mode.

If two words are written to the TXREG and then the

SLEEP

instruction is executed, the following will occur:

The ﬁrst word will immediately transfer to the

TSR register and transmit.

The second word will remain in TXREG register.

Flag bit TXIF will not be set.

When the ﬁrst word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and ﬂag bit TXIF will now be

set.

If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP and if the global interrupt

is enabled, the program will branch to the inter-

rupt vector (0004h).

Steps to follow when setting up Synchronous Slave

Transmission:

Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN, and clearing bit

CSRC.

Clear bits CREN and SREN.

If interrupts are desired, then set enable bit

TXIE.

If 9-bit transmission is desired, then set bit TX9.

Enable the transmission by setting bit TXEN.

If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

Start transmission by loading data to the

TXREG register.

Applicable Devices

61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67

12.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the synchronous master and slave

modes is identical except in the case of the SLEEP

mode. Also, enable bit SREN is a don't care in slave

mode.

If receive is enabled by setting bit CREN prior to the

SLEEP

instruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR

and if enable bit RCIE is set, the interrupt generated will

wake the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt vector

(0004h).

Steps to follow when setting up a Synchronous Slave

Reception:

Enable the synchronous master serial port by

setting bits SYNC and SPEN, and clearing bit

CSRC.

If interrupts are desired, then set enable bit

RCIE.

If 9-bit reception is desired, then set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCIF will be set when reception is com-

plete, and an interrupt will be generated if

enable bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

enable bit CREN.

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