www.austriamicrosystems.com/AS3647

1.5-4

32 - 37

AS3647/47B

Datasheet, Confidential - A p p l i c a t i o n I n f o r m a t i o n

PCB Layout Guideline

The high speed operation requires proper layout for optimum performance. Route the power traces first and try to min-

imize the area and wire length of the two high frequency/high current loops:

At the pin GND a single via (or more vias, which are closely combined) connects to the common ground plane. This

via(s) will isolate the DCDC high frequency currents from the common ground (as most high frequency current will flow

between Loop1 and Loop2 and will not pass the ground plane) - see the ‘island’ in Figure 32.

Figure 32. Layout recommendation

Note: If component placement rules allow, move all components close to the AS3647/47B to reduce the area and

length of Loop1 and Loop2.

ommended to filter high frequency noise for the power supply of AS3647/47B. This capacitor should be as close as

possible to the GND/VIN pins of AS3647/47B.

  

   

  

 

 

   

 





 



   !

"

 #!   ! !

$!  

 %



  &!  & "  &



 

 %

'

)* '

)* (

AS3647