© 2007 Microchip Technology Inc.
DS21191P-page 1
24AA128/24LC128/24FC128
Device Selection Table
Features:
• Single supply with operation down to 1.7V for
24AA128/24FC128 devices, 2.5V for 24LC128
devices
• Low-power CMOS technology:
- Write current 3 mA, typical
- Standby current 100 nA, typical
• 2-wire serial interface, I2C™ compatible
• Cascadable up to eight devices
• Schmitt Trigger inputs for noise suppression
• Output slope control to eliminate ground bounce
• 100 kHz and 400 kHz clock compatibility
• 1 MHz clock for FC versions
• Page write time 5 ms, typical
• Self-timed erase/write cycle
• 64-byte page write buffer <adjust per device>
• Hardware write-protect
• ESD protection >4000V
• More than 1 million erase/write cycles
• Data retention > 200 years
• Factory programming available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN and MSOP packages
• Pb-free and RoHS compliant
• Temperature ranges:
Description:
The Microchip Technology Inc. 24AA128/24LC128/
24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial
Electrically Erasable PROM (EEPROM), capable of
operation across a broad voltage range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device also has a page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads up to the 128K
boundary. Functional address lines allow up to eight
devices on the same bus, for up to 1 Mbit address
space. This device is available in the standard 8-pin
plastic DIP, SOIC (3.90 mm and 5.28 mm), TSSOP,
MSOP and DFN packages.
Block Diagram
*24XX128 is used in this document as a generic part number
for the 24AA128/24LC128/24FC128 devices.
Package Types
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA128
1.7-5.5V
400 kHz(1)
I
24LC128
2.5-5.5V
400 kHz
I, E
24FC128
1.7-5.5V
1 MHz(2)
I
Note 1:
100 kHz for VCC < 2.5V.
2:
400 kHz for VCC < 2.5V.
- Industrial (I):
-40
°C to +85°C
- Automotive (E):
-40
°C to +125°C
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
M
emory
C
ontrol
L
ogic
I/O
C
ontrol
L
ogic
I/O
A0 A1 A2
SDA
SCL
VCC
VSS
WP
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP/SOIC
TSSOP/MSOP*
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
DFN
A0
A1
A2
VSS
WP
SCL
SDA
5
6
7
8
4
3
2
1
VCC
Note: * Pins A0 and A1 are no-connects for the MSOP package only.
128K I2C™ CMOS Serial EEPROM
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
