RFD21733 datasheet(39/76 Pages) ETC2

39 / 76 page

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RFD21733 • FCC • IC

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RF Module

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KEYFOBs

The following timing diagrams show the operation of a logic transmitter and a logic receiver with the different hang

time options.

In the first diagram, the logic transmitter’s inputs are all asserted, and then sequentially de-asserted. There is a

small delay between the transmitter input going high and the corresponding output on the receiver going high, due

to the time required to transmit over the air.

Note that when the last input on the transmitter is de-asserted, there is a 500ms delay before the receiver de-

asserts its last output.

The second diagram shows the same operation at the transmitter, but with the receiver configured with a 20ms

hang time.

Note that shortly after the last input is de-asserted, the receiver updates its output state to turn off all outputs.

Communication between UART and Switch Logic Receiver/Transmitter

The Logic Receiver and Transmitter modes are able to communicate with a module operating in one of the UART

modes, which opens up a wide range of possible applications involving PC’s or embedded systems with serial

communications capability.

Logic Transmitter to UART

A Logic Transmitter (whether RFID or not) sends the state of its inputs as a single byte of data, followed by its

ESN as four bytes. A Mode 2 or Mode 3, Module or RFDANT in Serial UART can receive this packet and output

it as a binary stream to a PC serial port or an embedded microcontroller. The format of the data is:

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