5-4

FAST AND LS TTL DATA

SN54/74LS164

AC WAVEFORMS

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays

and Clock Pulse Width

Figure 2. Master Reset Pulse Width,

Master Reset to Output Delay and

Master Reset to Clock Recovery Time

Figure 3. Data Setup and Hold Times

CONDITIONS: MR = H

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

tPHL

tPLH

CP

Q

CP

Q

MR

trec

tW

tPHL

tW

I/fmax

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

CP

D

Q

ts(H)

th(H)

ts(L)

th(L)

tW

1/fmax

1.3 V

1.3 V

*

1.3 V