5-421

FAST AND LS TTL DATA

DUAL 4-BIT

ADDRESSABLE LATCH

The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control

inputs; these include two Address inputs (A0, A1), an active LOW Enable input

(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and

four outputs (Q0–Q3).

When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs

(Q0–Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and

E are both LOW. When CL is HIGH and E is LOW, the selected output

(Q0–Q3), determined by the Address inputs, follows D. When the E goes

HIGH, the contents of the latch are stored. When operating in the addressable

latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address

(A0, A1) could impose a transient wrong address. Therefore, this should be

done only while in the memory mode (E= CL = HIGH).

14

13

12

11

10

9

1

2

3

4

5

6

7

16

15

8

VCC

A0

CL

E

Db Q3b

Q1b

Q2b

Q0b

A1

Da

Q0a Q1a Q2a Q3a GND

CONNECTION DIAGRAM DIP (TOP VIEW)

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

PIN NAMES

LOADING (Note a)

HIGH

LOW

A0, A1

Address Inputs

0.5 U.L.

0.25 U.L.

Da, Db

Data Inputs

0.5 U.L.

0.25 U.L.

E

Enable Input (Active LOW)

1.0 U.L.

0.5 U.L.

CL

Clear Input (Active LOW)

0.5 U.L.

0.25 U.L.

Q0a – Q3a,

Q0b – Q3b

Parallel Latch Outputs (Note b)

10 U.L.

5 (2.5) U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40

µA HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial

(74) Temperature Ranges.

SN54/74LS256

DUAL 4-BIT

ADDRESSABLE LATCH

LOW POWER SCHOTTKY

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

16

1

D SUFFIX

SOIC

CASE 751B-03

4

5 6

7

9 10 11 12

3

2 1 15

14 13

Da E A0

A1

CL

Q0a Q1a Q2a Q3a

Q0b Q1b Q2b Q3b

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

E Db

A0

A1

CL