5-565

FAST AND LS TTL DATA

SN54/74LS490

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Clock Frequency

25

35

MHz

Figure 1

VCC = 5.0 V,

CL = 15 pF

tPLH

tPHL

Propagation Delay, CP to Q0

12

13

20

20

ns

Figure 1

VCC = 5.0 V,

CL = 15 pF

tPLH

tPHL

Propagation Delay, CP to Q1 or Q3

24

26

39

39

ns

Figure 3

VCC = 5.0 V,

CL = 15 pF

tPLH

tPHL

Propagation Delay, CP to Q2

32

36

54

54

ns

Figure 2

VCC = 5.0 V,

CL = 15 pF

tPHL

Propagation Delay, MR to Output

24

39

ns

Figure 2

tPLH

tPHL

Propagation Delay, MS to Output

24

20

39

36

ns

Figure 2

trec

trec

AC WAVEFORMS

Figure 1

Figure 2

Figure 3

*The number of Clock Pulses required between the tPHL and tPLH measurements can be determined from the Truth Table.

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

*CP

Q

MR & MS

CP

Q

MS

CP

QO, Q3

tPLH

tPHL

tPLH

tPHL

tW

tW

tW