AD5228BUJZ50-R2 datasheet(14/20 Pages) AD

14 / 20 page

AD5228

Rev. A | Page 14 of 20

LAYOUT AND POWER SUPPLY BIASING

POWER-UP AND POWER-DOWN SEQUENCES

It is always a good practice to use compact, minimum lead

length layout design. The leads to the input should be as direct

as possible with a minimum conductor length. Ground paths

should have low resistance and low inductance. It is also good

practice to bypass the power supplies with quality capacitors.

Low ESR (equivalent series resistance) 1 μF to 10 μF tantalum

or electrolytic capacitors should be applied at the supplies to

minimize any transient disturbance and to filter low frequency

ripple. Figure 39 illustrates the basic supply bypassing configu-

ration for the AD5228.

Because of the ESD protection diodes that limit the voltage

compliance at Terminals A, B, and W (Figure 39), it is

important to power on VDD before applying any voltage to

Terminals A, B, and W. Otherwise, the diodes are forward-

biased such that VDD is powered on unintentionally and can

affect other parts of the circuit. Similarly, VDD should be

powered down last. The ideal power-on sequence is in the

following order: GND, VDD, and VA/B/W. The order of powering

VA, VB, and VW is not important as long as they are powered on

after VDD. The states of the PU and PD pins can be logic high or

floating, but they should not be logic low during power-on.

VDD

GND

AD5228

μF

0.1

μF

Figure 40. Power Supply Bypassing

AD5228BUJZ50-R2 Datasheet(PDF) 14 Page - Analog Devices