RX64M datasheet(22/67 Pages) RENESAS

22 / 67 page

RX64M Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0173EJ0090 Rev.0.90

Page 22 of 67

Feb 28, 2014

Ethernet controller

REF50CK0, REF50CK1

Input

50-MHz reference clocks. These pins input reference signals for

transmission/reception timings in RMII mode.

RMII0_CRS_DV,

RMII1_CRS_DV

Input

Indicate that there are carrier detection signals and valid

receive data on RMII_RXD1 and RMII_RXD0 in RMII mode.

RMII0_TXD0, RMII0_TXD1,

RMII1_TXD0, RMII1_TXD1

Output

2-bit transmit data in RMII mode

RMII0_RXD0, RMII0_RXD1,

RMII1_RXD0, RMII1_RXD1

Input

2-bit receive data in RMII mode

RMII0_TXD_EN,

RMII1_TXD_EN

Output

Output pins for data transmit enable signals in RMII mode

RMII0_RX_ER,

RMII1_RX_ER

Input

Indicate an error has occurred during reception of data in RMII

mode.

ET0_CRS,

ET1_CRS

Input

Carrier detection/data reception enable pins

ET0_RX_DV,

ET1_RX_DV

Input

Indicate that there are valid receive data on ET_ERXD3 to

ET_ERXD0.

ET0_EXOUT,

ET1_EXOUT

Output

General-purpose external output pins

ET0_LINKSTA

ET1_LINKSTA

Input

Input link status from the PHY-LSI.

ET0_ETXD0 to ET0_ETXD3,

ET1_ETXD0 to ET1_ETXD3

Output

4 bits of MII transmit data

ET0_ERXD0 to ET0_ERXD3,

ET1_ERXD0 to ET1_ERXD3

Input

4 bits of MII receive data

ET0_TX_EN,

ET1_TX_EN

Output

Transmit enable pins. Function as signals indicating that

transmit data is ready on ET_ETXD3 to ET_ETXD0.

ET0_TX_ER,

ET1_TX_ER

Output

Transmit error pins. Function as signals notifying the PHY_LSI

of an error during transmission.

ET0_RX_ER,

ET1_RX_ER

Input

Receive error pins. Function as signals to recognize an error

during reception.

ET0_TX_CLK,

ET1_TX_CLK

Input

Transmit clock pins. These pins input reference signals for

output timings from ET_TX_EN, ET_ETXD3 to ET_ETXD0, and

ET_TX_ER.

ET0_RX_CLK,

ET1_RX_CLK

Input

Receive clock pins. These pins input reference signals for input

timings to ET_RX_DV, ET_ERXD3 to ET_ERXD0, and

ET_RX_ER.

ET0_COL, ET1_COL

Input

Input collision detection signals.

ET0_WOL, ET1_WOL

Output

Receive Magic packets.

ET0_MDC, ET1_MDC

Output

Output reference clock signals for information transfer via

ET_MDIO.

ET0_MDIO, ET1_MDIO

I/O

Input or output bidirectional signals for exchange of

management information between the RX64M Group and the

PHY-LSI.

Table 1.4

Pin Functions (5/8)

Classifications

Pin Name

I/O

Description

RX64M Datasheet(PDF) 22 Page - Renesas Technology Corp

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