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CS5333 Datasheet(PDF) 8 Page - Cirrus Logic

Part # CS5333
Description  24-Bit, 96 kHz Stereo A/D Converter?
PDF  20 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5333 Datasheet(HTML) 8 Page - Cirrus Logic

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CS5333
8
DS520PP1
SWITCHING CHARACTERISTICS (T
A = -10 to 70° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
Parameters
Symbol
Min
Typ
Max
Units
Input Sample Rate
Base Rate Mode
High Rate Mode
Fs
Fs
2
50
-
-
50
100
kHz
kHz
MCLK Pulse Width High
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width High
MCLK / LRCK = 384 or 192
21
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 384 or 192
21
-
-
ns
MCLK Pulse Width High
MCLK / LRCK = 256 or 128
31
-
-
ns
MCLK Pulse Width Low
MCLK / LRCK = 256 or 128
31
-
-
ns
Master Mode
SCLK Falling to LRCK Edge
tslrd
-20
-
20
ns
SCLK Falling to SDATA Valid
tsdo
0
-
20
ns
SCLK Duty Cycle
40
50
60
%
Slave Mode
LRCK Duty Cycle
-
50
-
%
SCLK Pulse Width Low
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
SCLK Period
Base Rate Mode
High Rate Mode
tsclkw
tsclkw
-
-
-
-
ns
ns
SCLK Falling to LRCK Edge
tslrd
-20
-
20
ns
SCLK Falling to SDATA Valid
Base Rate Mode
High Rate Mode
tdss
tdss
-
-
-
-
ns
ns
1
128
()Fs
----------------------
1
64
()Fs
------------------
1
(512)Fs
1
(256)Fs



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