DS1225Y

021998 2/8

READ MODE

The DS1225Y executes a read cycle whenever WE

(Write Enable) is inactive (high) and CE (Chip Enable)

and OE (Output Enable) are active (low). The unique

fines which of the 8192 bytes of data is to be accessed.

Valid data will be available to the eight data output driv-

put signal is stable, providing that CE and OE access

times are also satisfied. If CE and OE access times are

not satisfied, then data access must be measured from

the later occurring signal and the limiting parameter is

cess.

WRITE MODE

The DS1225Y executes a write cycle whenever the WE

and CE signals are active (low) after address inputs are

stable. The latter occurring falling edge of CE or WE will

determine the start of the write cycle. The write cycle is

terminated by the earlier rising edge of CE or WE. All

address inputs must be kept valid throughout the write

cycle. WE must return to the high state for a minimum

ated. The OE control signal should be kept inactive

(high) during write cycles to avoid bus contention. How-

ever, if the output drivers are enabled (CE and OE ac-

falling edge.

DATA RETENTION MODE

greater than 4.5 volts and write protects at 4.25 nominal.

additional support circuitry. The DS1225Y constantly

SRAM automatically write protects itself, all inputs be-

come “don’t care,” and all outputs become high imped-

power switching circuit connects the lithium energy

source to RAM to retain data. During power–up, when

connects the lithium energy source. Normal RAM oper-