DS1644LPM

041697 4/11

DS1644L REGISTER MAP – BANK1 Table 2

ADDRESS

DATA

FUNCTION

ADDRESS

FUNCTION

7FFF

–

–

–

–

–

–

–

–

YEAR

00–99

7FFE

X

X

X

–

–

–

–

–

MONTH

01–12

7FFD

X

X

–

–

–

–

–

–

DATE

01–31

7FFC

X

FT

X

X

X

–

–

–

DAY

01–07

7FFB

X

X

–

–

–

–

–

–

HOUR

00–23

7FFA

X

–

–

–

–

–

–

–

MINUTES

00–59

7FF9

OSC

–

–

–

–

–

–

–

SECONDS

00–59

7FF8

W

R

X

X

X

X

X

X

CONTROL

A

OSC = STOP BIT

R

=

READ BIT

FT =

FREQUENCY TEST

W

= WRITE BIT

X

=

UNUSED

NOTE:

All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK

The DS1644L is in the read mode whenever WE (write

enable) is high, and CE (chip enable) is low. The device

architecture allows ripple-through access to any of the

address locations in the NV SRAM. Valid data will be

input is stable, providing that the CE and OE access

times and states are satisfied. If CE or OE access times

are not met, valid data will be available at the latter of

is controlled by CE and OE. If the outputs are activated

CE and OE remain valid, output data will remain valid for

until the next address access.

WRITING DATA TO RAM OR CLOCK

The DS1644L is in the write mode whenever WE and

CE are in their active state. The start of a write is refer-

enced to the latter occurring high to low transition of WE

or CE. The addresses must be held valid throughout the

cycle. CE or WE must return inactive for a minimum of

OE signal will be high during a write cycle. However,

OE can be active provided that care is taken with the

data bus to avoid bus contention. If OE is low prior to

WE transitioning low the data bus can become active

with read data defined by the address inputs. A low tran-

goes active.