DS2172T datasheet(4/21 Pages) DALLAS

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DS2172

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DETAILED PIN DESCRIPTION Table 1

SYMBOL

TYPE

DESCRIPTION

1TL

Transmit Load. A positive-going edge loads the pattern generator with

the contents of the Pattern Set Registers. The MSB of the repetitive or

pseudorandom pattern appears at TDATA after the third positive edge of

TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should

be tied to VSS if not used. See Figure 8 for timing information.

AD0

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD1

I/O

Data Bus. An 8-bit multiplexed address/data bus.

TEST

Test. Set high to 3-state all output pins ( INT , ADx, TDATA, RLOS).

Should be tied to VSS to enable all outputs.

5VSS

Signal Ground. 0.0V. Should be tied to local ground plane.

AD2

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD3

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD4

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD5

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD6

I/O

Data Bus. An 8-bit multiplexed address/data bus.

AD7

I/O

Data Bus. An 8-bit multiplexed address/data bus.

VSS

Signal Ground. 0.0V. Should be tied to local ground plane.

VDD

Positive Supply. 5.0V.

BTS

Bus Type Select. Strap high to select Motorola bus timing; strap low to

select Intel bus timing. This pin controls the function of the RD (DS),

ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the

function listed in parenthesis ().

(DS)

Read Input (Data Strobe).

Chip Select. Must be low to read or write the port.

ALE(AS)

Address Latch Enable (Address Strobe). A positive going edge serves

to demultiplex the bus.

(R/ W )

Write Input (Read/Write).

INT

Alarm Interrupt. Flags host controller during conditions defined in

Status Register. Active low, open drain output.

VDD

Positive Supply. 5.0V.

VSS

Signal Ground. 0.0V. Should be tied to local ground plane.

Load Count. A positive-going edge latches the current bit and bit error

count into the user accessible BCR and BECR registers and clears the

internal count registers. LC is logically OR’ed with control bit PCR.4.

Should be tied to VSS if not used.

RLOS

Receive Loss Of Sync. Indicates the real time status of the receive

synchronizer. Active high output.

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