DS2480 datasheet(13/26 Pages) DALLAS

13 / 26 page

DS2480

042498 13/26

TIMING DIAGRAMS

This section explains the wave forms generated by the

DS2480 on the 1–Wire bus in detail. First the commu-

nication wave forms such as the Reset/Presence

Detect Sequence and the time slots are discussed.

After that follows a detailed description of the pulse

function under various conditions. The wave forms as

generated by the DS2480 may deviate slightly from

specifications found in the “Book of DS19xx iButton

Standards” or in data sheets of 1–Wire slave devices.

However, at a closer look one will find that all of the tim-

ing requirements are met.

1–WIRE COMMUNICATION WAVE FORMS

One of the major features of the DS2480 is that it

relieves the host from generating the timing of the

1–Wire signals and sampling the 1–Wire bus at the

appropriate times. How this is done for the reset/pres-

ence detect sequence is shown in Figure 6a. This

sequence is composed of four timing segments: the

reset low time tRSTL, the short/interrupt sampling offset

tSI, the presence detect sampling offset tPDT and a delay

time tFILL. The timing segments tSI, tPDT and tFILL com-

prise the reset high time tRSTH where 1–Wire slave

devices assert their presence or interrupt pulse. During

this time the DS2480 pulls the 1–Wire bus high with its

weak pull–up current.

The values of all timing segments for all 1–Wire speed

options are shown in the table. Since the reset/presence

sequence is slow compared to the time slots, the values

for regular and flexible speed are the same. Except for

the falling edge of the presence pulse all edges are con-

trolled by the DS2480. The shape of the uncontrolled

falling edge is determined by the capacitance of the

1–Wire bus and the number, speed and sink capability

of the slave devices connected.

Reset/Presence Detect Figure 6a

TESTING FOR SHORT AND/OR INTERRUPT

PRESENCE TESTING

UNCONTROLLED

FALLING EDGE

tSI

RESET/PRESENCE SEQUENCE

tRSTH

tRSTL

PRESENCE

PULSE

tFILL

TIME

SLOT

IDLE

TIME

tPDT

Speed

tRSTL

tSI

tPDT

tFILL

tRSTH

Regular

512

µs

512

µs

584

µs

Overdrive

µs

Flexible

512

µs

512

µs

584

µs

After having received the command code for generating

a reset/presence sequence, the DS2480 pulls the

1–Wire bus low for tRSTL and then lets it go back to 5V.

The DS2480 will now wait for the short/interrupt sam-

pling offset tSI to expire and then test the voltage on the

1–Wire bus to determine if there is a short or an interrupt

signal. If there is no short or interrupt (as shown in the

picture), the DS2480 will wait for tPDT and test the volt-

age on the 1–Wire bus for a presence pulse. Regardless

of the result of the presence test, the DS2480 will then

wait for tFILL to expire and then send the command

response byte to the host.

If the test for interrupt or short reveals a logic 0, the

DS2480 will wait for 4096

µs and then test the 1–Wire

bus again. If a logic 0 is detected, the 1–Wire bus is

shorted and a command response byte with the code for

SHORT will be sent immediately. If a logic 1 is detected,

the device will wait for tFILL to expire after which it will

send the command response byte with the code for an

alarming presence pulse. No additional testing for a

presence pulse will be done. The DS2480 will perform

the short/interrupt testing as described also at Over-

drive speed, although interrupt signaling is only defined

for regular speed.

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