MA28151

10/22

3.12 STATUS READ DEFINITION

In data communication systems it is often necessary to

examine the status of the active device to ascertain if errors

have occurred or other conditions that require the processor’s

attention. The MA28151 has facilities that allow the

programmer to read the status of the device at any time during

the functional operation. (Status update is inhibited during

status read).

A normal read command is issued by the CPU with CDN

high to accomplish this function.

Some of the bits in the Status Read Format have identical

meanings to external output pins so that the MA28151 can be

used in a completely polled or interrupt-driven environment.

TxRDY is an exception.

Note that status update can have a maximum delay of 28

clock periods from the actual event affecting the status.

3.13 STATUS READ FORMAT

D

7

DSR

D

6

SYNDET

BRKDET

D

5

FE

D

4

OE

D

3

PE

D

2

Tx

EMPTY

D

1

RxRDY

D

0

TxRDY

PARITY ERROR

The PE flag is set when the

parity error is detected. It is

reset by the ER bit of the

Command Instruction. PE does

not inhibit the operation of the

MA28151.

Note 1: TxRDY status bit has different meanings from the TxRDY output pin. The former

is not conditioned by CTS and TxEN, the latter is conditioned by both CTS and TxEN.

ie. TxRDY status bit 0 DB buffer empty

TxRDY pin out = DB buffer empty OR (CTSN = 0) OR (TxEN = 1)

Note 1

Same as I/O pins

OVERRUN ERROR

The OE flag is set when the

CPU does not read a character

before the next one becomes

available. It is reset by the ER

bit of the Command Instruction

OE does not inhibit operation

of the MA28151, however the

previously overrun character is

lost.

FRAMING ERROR (ASYNC

ONLY)

The FE flag is set when a valid

Stop bit is not detected at the

end of every character. It is

reset by the ER bit of the

Command Instruction. FE does

not inhibit the operation of the

MA28151.

DATA SET READY

Indicates that the DSR is at a

zero level.

Figure 13: Status Read Format