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SERIAL PROGRAMMING INTERFACE

ADS5542

SBAS308D – MAY 2004 – REVISED FEBRUARY 2007

In the event of an input voltage overdrive, the digital outputs go to the appropriate full scale level. For a positive

overdrive, the output code is 0x3FFF in straight offset binary output format, and 0x1FFF in 2's complement

output format. For a negative input overdrive, the output code is 0x0000 in straight offset binary output format

and 0x2000 in two's complement output format. These outputs to an overdrive signal are ensured through

design and characterization

The output circuitry of the ADS5542, by design, minimizes the noise produced by the data switching transients,

and, in particular, its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance and

adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in

the timing diagram of Figure 1. Care should be taken to ensure that all output lines (including CLKOUT) have

nearly the same load as D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply

voltage or temperature. Placing external resistors in series with the outputs is not recommended.

The timing characteristics of the digital outputs change for sampling rates below the 80 MSPS maximum

sampling frequency. Table 5 and Table 6 show the values of various timing parameters for lower sampling

frequenies.

Table 5. Timing Characteristics at Additional Sampling Frequencies

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

65

4.3

5.7

2

3

2.8

4.5

8.3

11.8

6.6

7.2

5.5

6.4

40

8.5

11

2.6

3.5

–1

1.5

8.9

14.5

7.5

8

7.3

7.8

20

17

25.7

2.5

4.7

–9.8

2

9.5

21.6

7.5

8

7.6

8

10

27

51

4

6.5

-30

-3

11.5

31

2

284

370

8

19

185

320

515

576

50

82

75

150

Table 6. Timing Characteristics at Additional Sampling Frequencies

CLKOUT Jitter,

CLKOUT, Rise Time

CLKOUT, Fall Time

Input-to-Output Clock Delay

Peak-to-Peak

(MSPS)

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

65

3.1

3.5

2.6

2.9

260

380

7.8

8.5

9.4

40

4.8

5.3

4

4.4

445

650

9.5

10.4

11.4

20

8.3

9.5

7.6

8.2

800

1200

13

15.5

18

10

16

20.7

25.5

2

31

52

36

65

2610

4400

537

551

567

The ADS5542 has internal registers for the programming of some of the modes described in the previous

sections. The registers should be reset after power-up by applying a 2 us (minimum) high pulse on RESET (pin

35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-k

Ω internal pullup

setting in the Serial Programing Interface section describe the programming of this register.

Table 2 shows the different modes and the bit values to be written to the register to enable them.

Note that some of these modes may modify the standard operation of the device and possibly vary the

performance with respect to the typical data shown in this data sheet.

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