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PI6C20400BLE Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6C20400BLE Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 11 page  1 www.pericom.com P-0.1 10/12/2011 PI6C20400B Block Diagram Pin Configuration Description Pericom Semiconductor's PI6C20400B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compat- ible with PCIe 1.0 and 2.0 specification. The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is low, the output clocks are Tristated. When PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated. Features Î Phase jitter filter for PCIe 3.0 application Î Four Pairs of Differential Clocks Î Low skew < 50ps Î Low jitter < 50ps cycle-to-cycle Î < 1 ps additive RMS phase jitter Î Output Enable for all outputs Î Outputs tristate control via SMBus Î Programmable PLL Bandwidth Î 100 MHz PLL Mode operation Î 100 - 400 MHz Bypass Mode operation Î 3.3V Operation Î Packaging (Pb-free and Green): -28-Pin SSOP (H28) -28-Pin TSSOP (L28) 1:4 Clock Driver for Intel PCIe® 3.0 Chipsets OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# DIV Output Control SMBus Controller PLL PLL_BW# SRC SRC# PLL/BYPASS# SCLK SDA OE_INV OE_0 & OE_3 SRC_STOP# PWRDWN# VDD_A VSS_A IREF OE_INV VDD OUT3 OUT3# OE_3 OUT2 OUT2# VDD PLL_BW# SRC_STOP# PWRDWN# 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD SRC SRC# VSS VDD OUT0 OUT0# OE_0 OUT1 OUT1# VDD PLL/BYPASS# SCLK SDA 11-0126 |
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