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IO10PDB0V0 Datasheet(PDF) 164 Page - Microsemi Corporation |
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IO10PDB0V0 Datasheet(HTML) 164 Page - Microsemi Corporation |
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164 / 197 page ![]() Pin Descriptions 5- 50 R e v i sio n 1 2 P10 TM0 TM3 TM3 P11 GNDA GNDA GNDA P12 VCCMAINXTAL VCCMAINXTAL VCCMAINXTAL P13 GNDLPXTAL GNDLPXTAL GNDLPXTAL P14 VDDBAT VDDBAT VDDBAT P15 PTEM PTEM PTEM P16 PTBASE PTBASE PTBASE R1 PCAP PCAP PCAP R2 SDD0 SDD0 SDD0 R3 ADC0 ABPS0 ABPS0 R4 ADC3 TM0 TM0 R5 NC ABPS2 ABPS2 R6 NC ADC1 ADC1 R7 NC VCC33ADC0 VCC33ADC0 R8 VCC15ADC0 VCC15ADC1 VCC15ADC1 R9 ADC10 ADC7 ADC7 R10 ABPS1 ABPS7 ABPS7 R11 NC ABPS4 ABPS4 R12 MAINXIN MAINXIN MAINXIN R13 MAINXOUT MAINXOUT MAINXOUT R14 LPXIN LPXIN LPXIN R15 LPXOUT LPXOUT LPXOUT R16 VCC33A VCC33A VCC33A T1 NCAP NCAP NCAP T2 ADC1 ABPS1 ABPS1 T3 ADC2 CM0 CM0 T4 NC GNDTM0 GNDTM0 T5 NC ADC0 ADC0 T6 NC VAREF0 VAREF0 T7 NC GND33ADC0 GND33ADC0 T8 GND15ADC0 GND15ADC1 GND15ADC1 Pin No. FG256 A2F060 Function A2F200 Function A2F500 Function Notes: 1. Shading denotes pins that do not have completely identical functions from density to density. For example, the bank assignment can be different for an I/O, or the function might be available only on a larger density device. 2. *: Indicates that the signal assigned to the pins as a CLKBUF/CLKBUF_LVPECL/CLKBUF_LVDS goes through a glitchless mux. In order for the glitchless mux to operate correctly, the signal must be a free-running clock signal. Refer to the ’Glitchless MUX’ section in the SmartFusion Microcontroller Subsystem User’s Guide for more details. |
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