DocID14914 Rev 2

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L6386AD

Electrical characteristics

15

3.3

Timing diagram

Figure 3. Input/output timing diagram

Symbol

Pin

Parameter

Test condition

Min

Typ

Max

Unit

Logic inputs

1, 2, 3

Low level logic voltage

1.5

V

High level logic voltage

3.6

V

High level logic input current

50

70

A

Low level logic input current

1

A

Sense comparator

Input offset voltage

-10

10

mV

6

Input bias current

0.2

A

2

Open drain low level output voltage

0.8

V

Comparator reference voltage

0.46

0.50

0.54

V

–



–



–

 I



–

-------------------------------------------------------------------------------------------------------

=

HIN

LIN

SD

HOUT

LOUT

DIAG

Note: SD active condition is latched until next negative IN edge.

D97IN522A