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A3P030 Datasheet(PDF) 81 Page - Microsemi Corporation |
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A3P030 Datasheet(HTML) 81 Page - Microsemi Corporation |
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81 / 210 page  ProASIC3 Flash Family FPGAs Re vi s i on 15 2 - 76 DDR Module Specifications Input DDR Module Figure 2-19 • Input DDR Timing Model Table 2-101 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B Input DDR Data CLK CLKBUF INBUF Out_QF (to core) FF2 FF1 INBUF CLR DDR_IN E A B C D Out_QR (to core) |
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