LP3907 datasheet(33/57 Pages) TI1

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LP3907

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SNVS511N – JUNE 2007 – REVISED AUGUST 2011

INTERRUPT STATUS REGISTER (ISRA) 0X02

This register informs the System Engineer of the temperature status of the chip.

D7-2

Name

—

Temp 125°C

—

Access

—

Data

Reserved

Status bit for thermal warning

Reserved

PMIC T>125°C

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reset

CONTROL 1 REGISTER (SCR1) 0X07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM

and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.

D6-4

Name

—

EN_DLY

—

FPWM2

FPWM1

ECEN

Access

—

R/W

—

R/W

Data

Reserved

Selects the preset

Reserved

Buck2 PWM /PFM Mode Buck 1 PWM /PFM

Reserved

delay sequence from

select

Mode select

EN_T assertion

0 – Auto Switch PFM -

(shown below)

PWM operation

1 – PWM Mode Only

Reset

Factory-Programmed

Default

EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION

Delay (ms)

EN_DLY<2:0>

Buck1

Buck2

LDO1

LDO2

000

001

1.5

010

1.5

011

1.5

100

1.5

101

1.5

110

1.5

111

BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10

This register controls the enables for the Bucks and LDOs.

Name

—

LDO2EN

—

LDO1EN

—

BK2EN

—

BK1EN

Access

—

R/W

—

R/W

—

R/W

—

R/W

Data

Reserved

0 – Disable

Reserved

0 – Disable

Reserved

0 – Disable

Reserved

0 – Disable

1 – Enable

Reset

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