MB40C318VPFV datasheet(10/16 Pages) FUJITSU

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MB40C318V

s TIMING DIAGRAM 2

Differential CLK input-demultiplex output (in-phase) mode

• CLKEP = CLKEN = 140 MHz (max)

• CLKA = CLKB = “L” (DVSS)

• CKSEL = “H” (AVDD)

• DSEL = “L” (DVSS)

•CE = “L” (AVSS)

•OE = “L” (DVSS)

• Differential CLK input — Solid line: CLKEP, Dotted line: CLKEN

•VINA input — Sampling at CLKEP rising

(CLKEN falling)

•DA0 to DA7 — Output (after 5 CLK + tpdM1 from Sampling) at CLKEP rising

(CLKEN falling)

•DB0 to DB7 — Output (after 6 CLK + tpdM1 from Sampling) at CLKEP rising

(CLKEN falling)

VOHD

VOLD

DA0 to DA7

Differential

CLK input

RESET input

VOHD

VOLD

− 10

or N

− 9

− 8

or N

− 9

− 8

or N

− 7

− 6

or N

− 7

− 4

or N

− 5

− 2

+ 1

or N

− 3

− 1

or N

− 2

− 3

or N

− 4

− 5

or N

− 6

− 7

or N

− 8

− 9

or N

− 10

− 9

or N

− 8

DB0 to DB7

VOHD

VOLD

CLKOA

VOHD

VOLD

CLKOB

VIHD

VILD

VIHD

VILD

1.5 V

DVDD

− 0.4 V

0.4 V

tpdM1O(typ)

tpdM1O(max)

tpdM1O(min)

tpdM1(typ)

tpdM1(min)

tpdM1(max)

tpdM1(typ)

tpdM1(max)

tpdM1(min)

+ 2

+ 3

DVDD

− 0.4 V

0.4V

DVDD

− 0.4 V

0.4V

TtWS

+ tWS−

tAD

− 3 N − 2 N − 1

+ 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10

− 10

or N

− 11

DVDDI

− 1.1 V

DVDDI

− 1.45 V

ALL “L” fix

VINA input

MB40C318VPFV Datasheet(PDF) 10 Page - fujitsu semiconductor

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