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MB40C958VPFV Datasheet(PDF) 3 Page - fujitsu semiconductor |
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MB40C958VPFV Datasheet(HTML) 3 Page - fujitsu semiconductor |
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3 / 13 page ![]() 3 MB40C958V s PIN DESCRIPTION Pin No. Symbol I/O Description 4 to 11 12 to 19 20 to 27 R0 to R7 G0 to G7 B0 to B7 I Data signal incoming terminal for Rch, Gch and Bch LSB: R0, G0, B0 MSB: R7, G7,B7 28 29 30 RCLK GCLK BCLK I Clock signal incoming terminal for Rch, Gch and Bch (TTL compatible) 47 CE I Power saving signal incoming terminal. Power saving enabled for High 48 DVDD — Digital power supply terminal (standard 5 V) 40, 46 AVDD — Analog power supply terminal (standard 5 V) 31 DVSS — Digital ground terminal 42, 44 AVSS — Analog ground terminal 36 VROUT O Rererence voltage output terminal (standard: 2 V) 1 37 35 RVRIN GVRIN BVRIN I Reference voltage incoming terminal for Rch, Gch and Bch (standard: 2 V) 2 39 34 RIREF GIREF BIREF — Reference resistor connection terminal for Rch, Gch and Bch 3 38 33 RVB GVB BVB — Connect >0.1 µF capacitor to the AVDD terminal 32 VA — Connect >0.1 µF capacitor to the AVSS terminal 45 43 41 ROUT GOUT BOUT O Analog signal output terminals for Rch, Gch and Bch |
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