AFE5807 datasheet(5/75 Pages) TI1

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AFE5807

www.ti.com

SLOS703C – SEPTEMBER 2010 – REVISED MAY 2013

PIN FUNCTIONS (continued)

DESCRIPTION

NO.

NAME

Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be connected

CW_QP_AMPINM

between CW_QP_AMPINM and CW_QP_OUTP. This pin becomes CH8 PGA negative output when PGA test mode

is enabled. Can be floated if not used.

Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor has to be connected

CW_QP_AMPINP

between CW_QP_AMPINP and CW_QP_OUTM. This pin becomes CH8 PGA positive output when PGA test mode is

enabled. Can be floated if not used.

Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be connected

CW_QP_OUTM

between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.

Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor has to be connected

CW_QP_OUTP

between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.

N8, P9~P7,

D1M~D8M

ADC CH1~8 LVDS negative outputs

P3~P1, N2

N9, R9~R7,

D1P~D8P

ADC CH1~8 LVDS positive outputs

R3~R1, N1

DCLKM

LVDS bit clock (6x or 7x) negative output

DCLKP

LVDS bit clock (6x or 7x) positive output

K7,

L5~L7,M5~M8,

DNC

Do not connect. Must leave floated

N4, N6

N3, N7

DVDD

ADC digital and I/O power supply, 1.8V

N5, P5, R5

DVSS

ADC digital ground

FCLKM

LVDS frame clock (1X) negative output

FCLKP

LVDS frame clock (1X) positive output

CH1~8 complimentary analog inputs. Bypass to ground with

≥ 0.015µF capacitors. The HPF response of the LNA

C9~C2

INM1…INM8

depends on the capacitors.

A9~A2

INP1...INP8

CH1~8 analog inputs. AC couple to inputs with

≥ 0.1µF capacitors.

ADC partial (fast) power down control pin with an internal pull down resistor of 100k

Ω. Active High. Either 1.8V or

PDN_ADC

3.3V logic level can be used.

VCA partial (fast) power down control pin with an internal pull down resistor of 20k

Ω. Active High, 3.3V logic level is

PDN_VCA

recommended.

Global (complete) power-down control pin for the entire chip with an internal pull down resistor of 20k

Ω. Active High,

PDN_GLOBAL

3.3V logic level is recommended.

0.5V reference output in the internal reference mode. Must leave floated in the internal reference mode. Adding test

REFM

point on PCB is recommended for monitoring the reference output.

1.5V reference output in the internal reference mode. Must leave floated in the internal reference mode. Adding test

REFP

point on PCB is recommended for monitoring the reference output.

RESET

Hardware reset pin with an internal pull-down resistor of 20k

Ω. Active high, 3.3V logic level is recommended.

SCLK

Serial interface clock input with an internal pull-down resistor of 20k

Ω, 3.3V logic level is recommended.

SDATA

Serial interface data input with an internal pull-down resistor of 20k

Ω, 3.3V logic level is recommended.

SDOUT

Serial interface data readout. High impedance when readout is disabled, 1.8V logic.

SEN

Serial interface enable with an internal pull up resistor of 20k

Ω. Active low, 3.3V logic level is recommended.

VCNTLM

Negative differential attenuation control pin. Common mode voltage is 0.75V

VCNTLP

Positive differential attenuation control pin. Common mode voltage is 0.75V

VHIGH

Bias voltage; bypass to ground with

≥1µF.

VREF_IN

ADC 1.4V reference input in the external reference mode; bypass to ground with 0.1µF.

K7, L5~L7,

DNC

Do not connect. Must leave floated

M5~M8, N4, N6

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