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TLV2548CPWR Datasheet(PDF) 34 Page - Texas Instruments |
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TLV2548CPWR Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 48 page  TLV2544, TLV2548 2.7V TO 5.5V, 12BIT, 200KSPS, 4/8CHANNEL, LOW POWER SERIAL ANALOGTODIGITAL CONVERTERS WITH AUTOPOWERDOWN SLAS198E − FEBRUARY 1999 − REVISED JUNE 2003 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DATA CODE INFORMATION Parts with a date code earlier than 31xxxxx have the following discrepancies: 1. Earlier devices react to FS input irrespective of the state of the CS signal 2. The earlier silicon was designed with SDO prereleased half clock ahead. This means in the microcontroller mode (FS=1) the SDO is changed on the rising edge of SCLK with a delay; and for DSP serial port (when FS is active) the SDO is changed on the falling edge of SCLK with a delay. This helps the setup time for processor input data, but may reduce the hold time for processor input data. It is recommended that a 100 pF capacitance be added to the SDO line of the ADC when interfacing with a slower processor that requires longer input data hold time. 3. For earlier silicon, the delay time is specified as: MIN NOM MAX UNIT VCC = 4.5 V SDO = 0 pF 16 Delay time, delay from SCLK falling edge (FS is active) or VCC = 4.5 V SDO = 100 pF 20 ns Delay time, delay from SCLK falling edge (FS is active) or SCLK rising edge (FS=1) to next SDO valid, td(SCLK-DOV). VCC = 2.7 V SDO = 0 pF 24 ns SCLK rising edge (FS=1) to next SDO valid, td(SCLK-DOV). VCC = 2.7 V SDO = 100 pF 30 This is because the SDO is changed at the rising edge in the up mode with a delay. This is the hold time required by the external digital host processor, therefore, a minimum value is specified. The newer silicon has been revised with SDO changed at the falling edge in the up mode with a delay. Since at least 0.5 SCLK exists as the hold time for the external host processor, the specified maximum value helps with the calculation of the setup time requirement of the external digital host processor. For an explanation of the DSP mode, reverse the rising/falling edges in item (2) above. |
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