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Copyright © 2010 Future Technology Devices International Limited

15

Document Reference No.: FT_000166

V2DIP2-64 VNCL2-64Q Development Module Datasheet Version 1.01

Clearance No.: FTDI# 155

Time

Description

Min

Typical

Max

Uni

t

t1

CLKOUT period

-

20.83

-

ns

t2

CLKOUT high period

9.38

10.42

11.46

ns

t3

CLKOUT low period

9.38

10.42

11.46

ns

t4

CLKOUT to RXF#

1

-

7.83

ns

t5

CLKOUT to read DATA valid

1

-

7.83

ns

t6

OE# to read DATA valid

1

-

7.83

ns

t7

CLKOUT to OE#

1

-

7.83

ns

t8

RD# setup time

12

-

-

ns

t9

RD# hold time

0

-

-

ns

t10

CLKOUT TO TXE#

1

-

-

ns

t11

Write DATA setup time

12

-

-

ns

t12

Write DATA hold time

0

-

-

ns

t13

WR# setup time

12

-

-

ns

t14

WR# hold time

0

-

-

ns

Table 3.9 - Synchronous FIFO Mode Read and Write Cycle Timing

In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An

external device synchronises to the CLKOUT output and it also has access to the output enable OE# input

to control data flow. An external device should drive output enable OE# low before pulling RD# line

down.

When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when

there is still data to be read. Similarly when bursts of data are to be written to the module WR# should

be kept low. TXE# remains low when there is still space available for the data to be written