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74HC40103D Datasheet(PDF) 13 Page - NXP Semiconductors |
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74HC40103D Datasheet(HTML) 13 Page - NXP Semiconductors |
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13 / 25 page ![]() 9397 750 13812 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data sheet Rev. 03 — 12 November 2004 13 of 25 Philips Semiconductors 74HC40103 8-bit synchronous binary down counter trem removal time MR to CP, PL to CP see Figure 10 VCC = 2.0 V 65 - - ns VCC = 4.5 V 13 - - ns VCC = 6.0 V 11 - - ns tsu set-up time PE to CP see Figure 11 VCC = 2.0 V 95 - - ns VCC = 4.5 V 19 - - ns VCC = 6.0 V 16 - - ns set-up time TE to CP see Figure 12 VCC = 2.0 V 190 - - ns VCC = 4.5 V 38 - - ns VCC = 6.0 V 33 - - ns set-up time Pn to CP see Figure 11 VCC = 2.0 V 95 - - ns VCC = 4.5 V 19 - - ns VCC = 6.0 V 16 - - ns th hold time PE to CP see Figure 11 VCC = 2.0 V 0 - - ns VCC = 4.5 V 0 - - ns VCC = 6.0 V 0 - - ns hold time TE to CP see Figure 12 VCC = 2.0 V 0 - - ns VCC = 4.5 V 0 - - ns VCC = 6.0 V 0 - - ns hold time Pn to CP see Figure 11 VCC = 2.0 V 0 - - ns VCC = 4.5 V 0 - - ns VCC = 6.0 V 0 - - ns fmax maximum clock frequency see Figure 7 VCC = 2.0 V 2.4 - - MHz VCC = 4.5 V 12 - - MHz VCC = 6.0 V 14 - - MHz Table 8: Dynamic characteristics …continued GND = 0 V; tr =tf = 6 ns; CL = 50 pF; see Figure 13. Symbol Parameter Conditions Min Typ Max Unit |
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