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GMS30C2116 Datasheet(PDF) 39 Page - Hynix Semiconductor |
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GMS30C2116 Datasheet(HTML) 39 Page - Hynix Semiconductor |
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39 / 322 page  ARCHITECTURE 1-19 1.6 Memory Organization (continued) Figure 1.12 shows the location of data and instructions in memory relative to a binary address n = ...xxx00 (x = 0 or 1). The memory organization is big-endian. 31 Byte n Byte n + 1 Byte n + 2 Byte n + 3 0 Halfword n Halfword n + 2 Byte n Byte n + 1 Halfword n + 2 Halfword n Byte n + 2 Byte n + 3 Word n High-Order Word n of Double-Word Low-Order Word n + 4 of Double-Word 1st Instruction Halfword 2nd Instruction Halfword (opt.) 3rd Instruction Halfword (opt.) Preceding Instruction 1st Instruction Halfword 2nd Instruction Halfword (opt.) 3rd Instruction Halfword (opt.) Figure 1. 12: Memory Organization At all data types, the most significant bit is located at the higher and the least significant bit at the lower bit position. |
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