W232

Document #: 38-07167 Rev. *E

Page 2 of 6

Overview

The W232 is a PLL-based clock driver designed for use in systems requiring a large number of synchronous timing signals. The clock

driver has output frequencies of up to 140 MHz and output-to-output skews of less than 100 ps. The W232 provides minimum

cycle-to-cycle and long-term jitter, which is of significant importance to meet the tight input-to-input skew budget in DIMM applications.

The W232 was specifically designed to accept SSFTG signals currently being used in motherboard designs to reduce EMI. Zero delay

buffers which are not designed to pass this feature through may cause skewing failures.

Output enable pins allow shutdown of output when they are not being used. This reduces EMI and power consumption.

Pin Definitions

Pin Name

Pin No.

(-09)

Pin No.

(-10)

Pin Type

Pin Description

CLK

24

24

I

Reference Input: Output signals Q0:9 are synchronized to this signal.

FBIN

13

13

I

Feedback Input: This input must be fed by one of the outputs (typically FBOUT)

to ensure proper functionality. If the trace between FBIN and FBOUT is equal

in length to the traces between the outputs and the signal destinations, then the

signals received at the destinations are synchronized to the CLK signal input.

Q0:8

3, 4, 5, 8, 9,

16, 17, 20, 21

3, 4, 5, 8, 9, 15,

16, 17, 20, 21

O

Outputs: The frequency and phase of the signals provided by these pins are

equal to the reference signal if properly laid out.

FBOUT

12

12

O

Feedback Output: Typically this is connected directly to the FBIN input with a

trace equal in length to the traces between outputs Q0:9 and the destination

points of these output signals.

AVDD

23

23

P

Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce

noise for optimal jitter performance.

AGND

1

1

G

Analog Ground Connection: Connect to common system ground plane.

VDD

2, 10, 15, 22

2, 10, 14 22

P

Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise

for optimal jitter performance.

GND

6, 7, 18, 19

6, 7, 18, 19

G

Ground Connections: Connect to common system ground plane.

OE0:4

11

–

I

to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.

OE

–

11

I

to GND (LOW, 0) outputs Q0:9 are disabled to a LOW state.

OE5:8

14

–

I

to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.

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