AT80SND2CMP3B datasheet(41/242 Pages) ATMEL

41 / 242 page

4341H–MP3–10/07

AT8xC51SND2C/MP3B

9.3

Registers

Table 9-4.

IEN0 Register

IEN0 (S:A8h) – Interrupt Enable Register 0

Reset Value = 0000 0000b

EAUD

EMP3

ET1

EX1

ET0

EX0

Bit Number

Bit

Mnemonic

Description

Enable All Interrupt Bit

Set to enable all interrupts.

Clear to disable all interrupts.

If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing

its interrupt enable bit.

EAUD

Audio Interface Interrupt Enable Bit

Set to enable audio interface interrupt.

Clear to disable audio interface interrupt.

EMP3

MP3 Decoder Interrupt Enable Bit

Set to enable MP3 decoder interrupt.

Clear to disable MP3 decoder interrupt.

Serial Port Interrupt Enable Bit

Set to enable serial port interrupt.

Clear to disable serial port interrupt.

ET1

Timer 1 Overflow Interrupt Enable Bit

Set to enable timer 1 overflow interrupt.

Clear to disable timer 1 overflow interrupt.

EX1

External Interrupt 1 Enable bit

Set to enable external interrupt 1.

Clear to disable external interrupt 1.

ET0

Timer 0 Overflow Interrupt Enable Bit

Set to enable timer 0 overflow interrupt.

Clear to disable timer 0 overflow interrupt.

EX0

External Interrupt 0 Enable Bit

Set to enable external interrupt 0.

Clear to disable external interrupt 0.

AT80SND2CMP3B Datasheet(PDF) 41 Page - ATMEL Corporation

AT80SND2CMP3B Datasheet(HTML) 41 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL