7

ICS9148-02

Notes:

1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.

y

t

i

l

a

n

o

i

t

c

n

u

FU

P

C

,

I

C

P

F

_

I

C

P

M

A

R

D

SF

E

RC

I

P

A

O

I

z

H

M

4

2

n

o

i

t

c

e

l

e

S

z

H

M

8

4

n

o

i

t

c

e

l

e

S

e

t

a

t

s

i

r

TZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

HZ

-

I

H

e

d

o

m

t

s

e

T2

/

K

L

C

T

1

4

/

K

L

C

T

1

2

/

K

L

C

T

1

K

L

C

T

1

K

L

C

T

1

4

/

K

L

C

T

1

2

/

K

L

C

T

1

Byte 1: CPU, 24/48 MHz Clock Register

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Byte 2: PCICLK Clock Register

Byte 4: SDRAM Clock Register

Notes: 1 = Enabled; 0 = Disabled, outputs held low

Notes: 1 = Enabled; 0 = Disabled, outputs held low

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B8

1

)

t

c

a

n

I

/

t

c

A

(

F

_

K

L

C

I

C

P

5

t

i

B6

11

)

t

c

a

n

I

/

t

c

A

(

5

K

L

C

I

C

P

4

t

i

B4

11

)

t

c

a

n

I

/

t

c

A

(

4

K

L

C

I

C

P

3

t

i

B3

11

)

t

c

a

n

I

/

t

c

A

(

3

K

L

C

I

C

P

2

t

i

B2

11

)

t

c

a

n

I

/

t

c

A

(

2

K

L

C

I

C

P

1

t

i

B1

11

)

t

c

a

n

I

/

t

c

A

(

1

K

L

C

I

C

P

0

t

i

B9

1

)

t

c

a

n

I

/

t

c

A

(

0

K

L

C

I

C

P

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B-

1

d

e

v

r

e

s

e

R

5

t

i

B-

1

d

e

v

r

e

s

e

R

4

t

i

B-

1

d

e

v

r

e

s

e

R

3

t

i

B-

1

d

e

v

r

e

s

e

R

2

t

i

B-

1

d

e

v

r

e

s

e

R

1

t

i

B-

1

d

e

v

r

e

s

e

R

0

t

i

B-

1

d

e

v

r

e

s

e

R

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B3

21

)

t

c

a

n

I

/

t

c

A

(

z

H

M

4

2

/

8

4

6

t

i

B2

21

)

t

c

a

n

I

/

t

c

A

(

z

H

M

4

2

/

8

4

5

t

i

B-

1

d

e

v

r

e

s

e

R

4

t

i

B-

1

d

e

v

r

e

s

e

R

3

t

i

B8

31

)

t

c

a

n

I

/

t

c

A

(

3

K

L

C

U

P

C

2

t

i

B9

31

)

t

c

a

n

I

/

t

c

A

(

2

K

L

C

U

P

C

1

t

i

B1

41

)

t

c

a

n

I

/

t

c

A

(

1

K

L

C

U

P

C

0

t

i

B2

41

)

t

c

a

n

I

/

t

c

A

(

0

K

L

C

U

P

C

Byte 3: SDRAM Clock Register

Notes: 1 = Enabled; 0 = Disabled, outputs held low

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B6

21

)

t

c

a

n

I

/

t

c

A

(

7

M

A

R

D

S

6

t

i

B7

21

)

t

c

a

n

I

/

t

c

A

(

6

M

A

R

D

S

5

t

i

B9

21

)

t

c

a

n

I

/

t

c

A

(

5

M

A

R

D

S

4

t

i

B0

31

)

t

c

a

n

I

/

t

c

A

(

4

M

A

R

D

S

3

t

i

B2

31

)

t

c

a

n

I

/

t

c

A

(

3

M

A

R

D

S

2

t

i

B3

31

)

t

c

a

n

I

/

t

c

A

(

2

M

A

R

D

S

1

t

i

B5

31

)

t

c

a

n

I

/

t

c

A

(

1

M

A

R

D

S

0

t

i

B6

31

)

t

c

a

n

I

/

t

c

A

(

0

M

A

R

D

S

Select Functions

Note: PWD = Power-Up Default