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ICS9148-32

Technical Pin Function Descriptions

VDD, VDD (1,2,3)

This is the power supply to the internal core logic of the

device as well as the clock output buffers for REF(0:2),

PCICLK_F, PCICLK(0:6),48MHz0,48MHz1.

This pin operates at 3.3V volts. Clocks from the listed buffers

that it supplies will have a voltage swing from Ground to this

level. For the actual guaranteed high and low voltage levels

for the Clocks, please consult the DC parameter table in this

data sheet.

VDDL(1,2)

This is the power supply for the CPUCLK (0:3) and IOAPIC

output buffers. The voltage level for these outputs may be

2.5 or 3.3volts. Clocks from the buffers that each supplies will

have a voltage swing from Ground to this level. For the actual

Guaranteed high and low voltage levels of these Clocks,

please consult the DC parameter table in this Data Sheet.

GND,GND(1,2,3)

This is the ground to the internal core logic of the device as

well as the clock output buffers for REF(0:2), PCICLK_F,

PCICLK(0:6),48MHz0,48MHz1.

GNDL(1,2)

This is the ground for the CPUCLK (0:3) and IOAPIC output

buffers.

X1

This input pin serves one of two functions. When the device

is used with a Crystal, X1 acts as the input pin for the

reference signal that comes from the discrete crystal. When

the device is driven by an external clock signal, X1 is the

device input pin for that reference clock. This pin also

implements an internal Crystal loading capacitor that is

connected to ground. With a nominal value of 33pF no

X2

This Output pin is used only when the device uses a Crystal

as the reference frequency source. In this mode of operation,

X2 is an output signal that drives (or excites) the discrete

Crystal. The X2 pin will also implement an internal Crystal

loading capacitor nominally 33pF.

CPUCLK(0:3)

These Output pins are the Clock Outputs that drive processor

and other CPU related circuitry that requires clocks which are

in tight skew tolerance with the CPU clock. The voltage

swing of these Clocks is controlled by the Voltage level

applied to the VDDL2 pin of the device. See the Functionality

Table for a list of the specific frequencies that are available

for these Clocks and the selection codes to produce them.

48MHz

This is a fixed frequency Clock output that is typically used

to drive USB devices.

24/48MHz

Fixed frequency clock output. 24MHz output if Pin1=1 at

power up. 48MHz if pin1=0 at power up.

IOAPIC(0:1)

This Output is a fixed frequency Output Clock that runs at

the Reference Input (typically 14.31818MHz) . Its voltage

level swing is controlled by VDDL1 and may operate at 2.5 or

3.3volts.

REF0/SEL48#

This is an input pin during power up only. During power up if

high, then pin 23 is a 24MHz fixed clock during normal

operation. If Low during power up, pin 23 is a 48MHz fixed

clock during normal operation. During normal operation, REF0

is an output which is a fixed frequency running at 14.318MHz.

REF(1:2)

The REF Outputs are fixed frequency Clocks that run at the

same frequency as the Input Reference Clock X1 or the

Crystal (typically 14.31818MHz) attached across X1 and X2.

PCICLK_F

This Output is equal to PCICLK(0:6) and is FREE RUNNING,

and will not be stopped by PCI_STOP#.

PCICLK(0:6)

These Output Clocks generate all the PCI timing requirements

for a Pentium/Pro based system. They conform to the current

PCI specification. They run at 33.3 MHz.

SEL 100/66.6#

This Input pin controls the frequency of the Clocks at the

CPUCLK, PCICLK and SDRAM output pins. If a logic “1”

value is present on this pin, the 100MHz Clock will be selected.

If a logic “0” is used, the 66.6MHz frequency will be selected.

The PCI clock is multiplexed to be 33.3MHz for both select

cases. PCI is synchronous at the rising edge of PCI to the

CPU rising edge (with the skew making CPU early).